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IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com
8
Model
I/O Register Bits
1
IOS-EP201
TTL Channels 0 to 47
IOS-EP202
Differential/RS485 Channels 0 to 23
IOS-EP203
TTL Channels
0 to 23
Differential /RS485
Channels 12 to 23
IOS-EP204
Differential/LVDS Channels 0 to 23
The external clock pin is an LVTTL
(NOT 5V TOLERANT)
input that
connects directly to a global clock input on the Altera FPGA. In addition,
several buffered I/O are routed to global input clock pins. Table 2.3
summarizes the buffered I/O are can be used for global input signals for
each IOS-EP2 Series model
. Note that modification of the example vhdl file
is required to utilize the additional global inputs.
Model
Buffered Global Inputs
1
IOS-EP201
TTL Channels 18, 22, & 46
IOS-EP202
RS485 Channels 9, 11, & 23
IOS-EP203
TTL Channels
18 & 22
RS485 Channel 23
IOS-EP204
LVDS Channels 9, 11, & 23
The board is non-isolated, since there is electrical continuity between the
logic and field I/O grounds. As such, the field I/O connections are not
isolated from the system. Care should be taken in designing installations
without isolation to avoid noise pickup and ground loops caused by multiple
ground connections.
Table 2.2:
IOS-EP2 Model
Channel Assignments
1. Refer to Table 2.1 for I/O
pin assignments.
Table 2.3:
IOS-EP2 Model
Global Clock Signals
1. These buffered I/O are
connected to global input pins
on the FPGA. Modification of
the Example Design is
required to use the global
inputs.
Non-Isolation
Considerations