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AP512 ACROPACK

USER

’S MANUAL

Acromag, Inc. Tel: 248-295-0310

- 24 - http://www.acromag.com

- 24 -

https://www.acromag.com

mode if any interrupts are pending.

5

1

0 = Disable the Receive Xoff Interrupt 1 = Enable the
Receive Xoff Interrupt

When software flow control in enabled, and one or two
sequential receive data characters match the
preprogrammed Xoff 1-2 values an interrupt will be issued.

6

1

0 = Disable RTS Interrupt 1 = Enable RTS Interrupt.

This Interrupt is generated when the RTS pin transitions
from a logic 0 to a logic 1. RTS is not output by this
module. Instead RTS is used to enable the transmitter of
the port. This interrupt should always be disabled.

7

1

0 = Disable CTS Interrupt 1 = Enable CTS Interrupt.

This interrupt will be issued when the CTS pin transitions
from a logic 0 to a logic 1. Since CTS is not used on this
module, this interrupt should always be disabled.

Bits 4 to 7 are only programmable when the EFR

bit 4 is set to “1”. A power

-

up or system reset sets all IER bits to 0 (bits 7-0 forced low).

3.2.6 ISR - Interrupt Status Register (READ Only)

The Interrupt Status Register is used to indicate that a prioritized interrupt is
pending and the type of interrupt that is pending. Six levels of prioritized
interrupts are provided to minimize software interaction. Performing a read
cycle on the ISR will provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowledged until the
pending interrupt is serviced. Whenever the interrupt status register is
read, the interrupt status is cleared.  Note, only the current pending
interrupt is cleared by the read.  A lower level interrupt may be seen after
re-reading the interrupt status bits.

The following interrupt source table shows the data values (bit 0-5) for the
six prioritized interrupt levels and the interrupt sources associated with each
of these interrupts.

Table 3.7 Interrupt source

PRIORITY

LEVEL

ISR BITS

Bit5 to Bit0

Source of the Interrupt

1

000110

Receiver Line Status (see LSR bits 1-4)

2

000100

Received Data Ready or Trigger Level
reached.

2

001100

Receive Data Time Out.

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Содержание AcroPack AP512

Страница 1: ...Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Email solutions acromag com Copyright 2016 Acromag Inc Printed in the USA Data and specifica...

Страница 2: ...ure 1 1 AP512 Block Diagram 5 1 3 1 Ordering Information 5 Table 1 1 Ordering Options 5 1 3 2 Key Features 5 1 3 3 Key Features PCIe Interface 6 1 4 Signal Interface Products 6 1 5 Software Support 6...

Страница 3: ...Interrupt Enable Register R W 23 Table 3 6 Interrupt Enable Register 23 3 2 6 ISR Interrupt Status Register READ Only 24 Table 3 7 Interrupt source 24 3 2 7 FCR FIFO Control Register WRITE Only 25 Tab...

Страница 4: ...iderations 36 5 3 1 Operating Temperature 36 5 3 2 Other Environmental Requirements 37 5 3 2 1 Relative Humidity 37 5 3 2 2 Isolation 37 5 3 3 Vibration and Shock Standards 37 5 3 4 EMC Directives 37...

Страница 5: ...keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag 1 2 1 Trademark Trade Name and Copyrig...

Страница 6: ...nated ports please consult the factory There is no support for internal biasing resistors Figure 1 1 AP512 Block Diagram Exar 17V354 UART Mini PCIe Connector PCIe x1 ADM2682E Isolated RS 422 485 Trans...

Страница 7: ...as the clock source and can be set to be a single shot or re triggerable and is capable of generating an interrupt 1 3 3 Key Features PCIe Interface PCIe Bus The AP module includes a PCI Express Gener...

Страница 8: ...is composed of VxWorks real time operating system libraries for all AcroPack modules VPX I O board products and PCIe I O Cards The software is implemented as a library of C functions which link with...

Страница 9: ...etic or radioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the Acromag Limited Warranty 2 1...

Страница 10: ...rovided to prevent a temperature rise above the maximum operating temperature 2 3 Board Configuration Power should be removed from the board when installing AP modules cables termination panels and fi...

Страница 11: ...ted GND_A 1 RSVD ISOL 4 RSVD ISOL 3 RSVD ISOL 6 Field I O 3 3 2 2 RXD _A 5 RSVD ISOL 8 RSVD ISOL 7 RSVD ISOL 10 Field I O 5 5 3 3 RXD _A 9 RSVD ISOL 12 RSVD ISOL 11 RSVD ISOL 14 Field I O 7 7 4 4 TXD...

Страница 12: ...VD ISOL 37 RSVD ISOL 40 RSVD ISOL 39 RSVD ISOL 42 RSVD ISOL 41 RSVD ISOL 44 RSVD ISOL 43 RSVD ISOL 46 RSVD ISOL 45 RSVD ISOL 48 RSVD ISOL 47 RSVD ISOL 50 RSVD ISOL 49 Field I O 26 26 38 47 Isolated GN...

Страница 13: ...AP512 Module Function 69 RSVD ISOL 72 RSVD ISOL 71 RSVD ISOL 74 Field I O 37 37 19 19 RXD _D 73 RSVD ISOL 76 RSVD ISOL 75 RSVD ISOL 78 Field I O 39 39 20 20 RXD _D 77 RSVD ISOL 80 RSVD ISOL 79 RSVD IS...

Страница 14: ...rking AC rms or DC isolation from each other Note Not all AcroPack carriers are able to maintain this level of isolation Consult the AcroPack carrier documentation for supported isolation voltages 2 7...

Страница 15: ...ot supported USB_D USB_D WAKE LED_WPAN LED_WLAN LED_WWAN W_DISABLE COEX1 COEX2 UIM_C4 UIM_C8 Note 2 UIM_PWR UIM_RESET UIM_CLK UIM_VPP UIM_DATA SIM card for cell signals may be available on some AcroPa...

Страница 16: ...dress and system interrupt request are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCIe bus configuration access is used to access the...

Страница 17: ...CI Configuration Registers Address Offset D31 D24 D23 D16 D15 D8 D7 D0 0x00 Device ID 0x0354 Vendor ID 0x13A8 0x04 Status Command 0x08 Class Code 0x070002 Rev ID Current REV 0x0C BIST Header Latency C...

Страница 18: ...Comment 0x0000 0x000F UART 0 Registers See Table 3 4 0x0010 0x007F Reserved 0x0080 0x009A Device Configuration Registers See Table 3 3 0x009B 0x00FF Reserved Reserved 0x0100 0x01FF UART 0 FIFOs 256 by...

Страница 19: ...two methods to load transmit data and unload receive data from each UART channel First there is a transmit data register and receive data register for each UART channel as shown in Table 3 2 set to e...

Страница 20: ...when writing to that address and receive data is unloaded from the RHR register when reading that address Both THR and RHR registers are 16C550 compatible in 8 bit format so each bus operation can onl...

Страница 21: ...Register which resets LSR bit 0 low If the character is not read prior to a new character transfer between the receiver shift register and the receiver buffer register the overrun error status indica...

Страница 22: ...rnal sampling clock suitable for synchronization to the desired baud rate The output of the baud generator RCLK is sixteen times the baud rate Two 8 bit divisor latch registers per port are used to st...

Страница 23: ...rt bit When the start bit is detected a counter is reset and counts the 16x sampling clock to 7 1 2 the center of the start bit The receiver then counts from 0 to 15 to sample the next bit near its ce...

Страница 24: ...Disable Interrupt 1 Enable Interrupt This interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared when the FIFO drops below the trigger level in the FIFO mode of...

Страница 25: ...up or system reset sets all IER bits to 0 bits 7 0 forced low 3 2 6 ISR Interrupt Status Register READ Only The Interrupt Status Register is used to indicate that a prioritized interrupt is pending an...

Страница 26: ...is write only register is used to enable and clear the FIFO buffers set the transmit receive FIFO trigger levels and select the type of DMA signaling Table 3 8 FIFO Control Register FCR BIT FUNCTION 0...

Страница 27: ...ine Control Register Read Write The Line Control Register is used to specify the asynchronous data communication format The word length the number of stop bits and the parity are selected by writing t...

Страница 28: ...For example if the following sequence is used no invalid characters are transmitted due to the presence of the break 1 Load a zero byte in response to the Transmitter Holding Register Empty THRE statu...

Страница 29: ...responding port to issue an interrupt Table 3 10 Modem Control Register MCR Bit FUNCTION PROGRAMMING 0 Data Terminal Ready Output Signal DTR 0 DTR Not Asserted Inactive 1 DTR Asserted Active 1 Ready t...

Страница 30: ...ROGRAMMING 0 Data Ready DR 0 Not Ready reset low by CPU Read of RHR or FIFO 1 Data Ready set high when character received and transferred into the RHR or FIFO 1 Overrun Error OE 0 No Error 1 Indicates...

Страница 31: ...host CPU during the first LSR read Only one 0 character is loaded into the FIFO when BI occurs 5 Transmitter Holding Register Empty THRE 0 Not Empty 1 Empty indicates that the channel is ready to acc...

Страница 32: ...r up or system reset sets all LSR bits to 0 except bits 5 and 6 which are high 3 2 11 MSR Modem Status Register Read Write The Modem Status Register MSR provides the host CPU with an indication on the...

Страница 33: ...termined by the corresponding input signal All other bits are not used 3 2 12 SCR Scratch Pad Read Write This 8 bit read write register has no effect on the operation of either serial channel It is pr...

Страница 34: ...Xoff1 and Xoff2 4 Enhanced Function Control 0 Disable and latch the Enhanced Functions the IER bits 4 7 ISR bits 4 5 FCR bits 4 5 MCR bits 5 7 This feature prevents existing software from altering or...

Страница 35: ...or remote buffer overflow indication When automatic CTS hardware flow control is enabled a CTS transition from logic 0 to a logic 1 to indicate a flow control request ISR bit 5 will be set to a logic...

Страница 36: ...ce Procedure CAUTION POWER MUST BE TURNED OFF BEFORE SERVICING BOARDS Before beginning repair be sure that all of the procedures in the Preparation for Use section have been followed Also refer to the...

Страница 37: ...duction cooled application with an AcroPack module will require purchase of the Heatsink AP CC 01 Table 5 1 Model ID Summarized below are the expected current draws for each of the specified power sup...

Страница 38: ...designed to pass the following Vibration and Shock standards Vibration Sinusoidal Operating Designed to comply with IEC 60068 2 6 10 500Hz 5G 2 Hours axis Vibration Random Operating Designed to compl...

Страница 39: ...using MIL HDBK 217F FN2 Per MIL HDBK 217 Ground Benign Controlled GBGC Temperature MTBF Hours MTBF Years Failure Rate FIT1 25 C 6 460 240 737 5 154 8 40 C 3 982 636 454 6 251 1 1 FIT is Failures in 1...

Страница 40: ...8 295 0310 39 http www acromag com 39 https www acromag com Appendix A AP CC 01 Heatsink Kit Installation This example will show how to install the AP CC 01 Heatsink kit with an APCe7020 carrier AP CC...

Страница 41: ...S MANUAL Acromag Inc Tel 248 295 0310 40 http www acromag com 40 https www acromag com 1 Install two standoffs and secure with two screws 2 Install the AcroPack module 3 Install the Heatsink and secur...

Страница 42: ...2 ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 41 http www acromag com 41 https www acromag com 4 AP CC 01 Installation is complete Note Make sure the thermal pad is making contact with the UAR...

Страница 43: ...ory of whose contents are lost when power is removed Yes No Type SRAM SDRAM etc UART Internal Registers FIFOs SRAM Size 4k bytes User Modifiable Yes No Function UART Communication Process to Sanitize...

Страница 44: ...marized in the table below Release Date DD MMM YYYY Version EGR DOC Description of Revision 30 AUG 2016 Prelim DWR Initial Preliminary Version 15 DEC 2016 A DWR ARP Initial Acromag Release 18 JUNE 201...

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