1 -
1
4
1 -
1
4
1 -
1
4
1 -
1
4
1 -
1
4
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
◎
◎
◎
◎
◎
Figure 4. Advanced Chipset Features
CMOS Setup Utility-Copyright(C) 1984-2001 Award Software
Advanced Chipset Features
This section allows you to configure the system based on
the specific features of the installed chipset. This chipset
manages bus speeds and access to system memory resources,
such as DRAM and external cache. It also coordinates
communications of the PCI bus. It must be stated that these
items should never need to be altered. The default settings
have been chosen because they provide the best operating
conditions for your system. The only time you might
consider making any changes would be if you discovered that
data was lost while using your system.
DRAM Clock / Drive Control
Press Enter
Item Help
AGP & P2P Bridge Control
Press Enter
CPU & PCI Bus Control
Press Enter
Menu Level
Chipset Register Adjust
Press Enter
Memory Hole
Disabled
System BIOS Cacheable
Disabled
Video RAM Cacheable
Disabled
←→↑↓
: Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F1:General Help F5:Previous Values F6:Fail-Safe Defaults
F7:Optimized Defaults
CMOS Setup Utility-Copyright (C) 1984-2001 Award Software
DRAM Clock / Drive Control
Current FSB Frequency
133MHz
Item Help
Current DRAM Frequency
166MHz
DRAM Clock
By SPD
Menu Level
DRAM Timing
By SPD
*SDRAM CAS Latency
2.5
*Bank Interleave
Disabled
*Precharge to Active(Trp)
3 T
*Active to Precharge(Tras)
6 T
*Active to CMD(Trcd)
3 T
*DRAM Queue Depth
4 Level
DRAM Command Rate
2T Command
←→↑↓
: Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F1:General Help F5:Previous Values F6:Fail-Safe Defaults
F7:Optimized Defaults
2.4 Advanced Chipset Features