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PAD128 Manual
Page 6-8
Manual MPAD128.D1g
Non-FIFO Polling
This is something of a misnomer, as the FIFO is always enabled. Basically, we will
only be using the FIFO as if it were a single sample deep. That is, each time a data
value goes in, it will be read out.
Initialize the card as above, with Pause set for each point.
Start a conversion: Base + 10 bit 0
Wait for End-of-Conversion: Base + 10 bit 0
Read the Data: Base + 18
Loop to “Start a Conversion”
"Wait for End-of-Conversion" is a loop that polls bit 0 of the A/D status register. When
the bit changes from 1 to 0, the conversion is complete.
The data will be in the format determined by bit 5 of base +10.
FIFO Polling
This acquisition method uses the FIFO in a polling manner, with the onboard counter
performing the start conversions.
Initialize as above, with no Pause bits, and set Loop on the last point.
Start a Conversion: Base + 10 bit 0
Wait for FIFO full Base + 14 bits F-B
Read the Data Base + 18
Loop to “Wait for FIFO full”
"Wait for FIFO Full" is a loop that reads the most significant 5 bits of Base + 14 to
determine how many samples are in the FIFO. When it is full (enough) the program
reads out that many samples. A typical example would be to read 30 points of data each
time the FIFO reached 30 points. This allows time for two more samples to enter the
FIFO while the 30 data samples are being read, preventing lost data. A slower computer
might want more headroom, and would read out fewer samples at a time.
Once enough data has been read, the Stop bit at Base+10 bit 0 is cleared to 0, halting
the process.
FIFO with Interrupt
FIFO with Sync
FIFO with Timer
FIFO with Watchdog
All of these modes and many more can be used with this A/D chip. Please refer to the
LM12H458 chip specification for more information on using these advanced features.