Manual 104-QUAD-8
14
Data Registers (0, 2, 4, 8, A, C, E)h:
These registers are read to retrieve the current count from the channel, and written to set the Preset
Register and the Filter Clock Prescalers.
To get the count from Channel 1 (Data register 0) you would first write 11h to the control register at
address 1. Three reads are then required to get the current count from data register 0. The first read
returns the Least Significant Byte and the last read returns the Most Significant Byte.
In order to write to the Preset Register first write 11h to the control register. Then perform three writes to
the data register. The first write is the Least Significant Byte, and the last write is the Most Significant
Byte.
In order to write to the Filter Clock Prescaler first write 11h to the control register. Then write one byte
to the data register with the desired PSC value. Then write 19h to the control register.
Control Registers (1, 3, 5, 7, 9, B, D, F)h:
The control registers all correspond to the data register that is one address below it.
The control register is used for the following operations:
Reading the Flag Register;
Resetting the BP (three byte data pointer) and flags;
Setting the PSC (filter clock factor n) and PR (preset count);
Initial setup of the Counter Mode Register, Input/Output Control Register and Index Control
Register.
Reading the FLAG Register:
Bit 0 BT:
Borrow Toggle flip-flop. Toggles every time the counter underflows.
Bit 1 CT:
Carry Toggle flip-flop. Toggles every time the counter overflows.
Bit 2 CPT :
Compare Toggle flip-flop. Toggles every time the counter is equal to the Preset
Register.
Bit 3 S:
Sign flag. Set to 1 when counter underflows and reset to 0 when it overflows.
Bit 4 E:
Error flag. Set to 1 when excessive noise is present at the count inputs in
quadrature mode. Ignore in other modes.
Bit 5 U/D:
Up/Down flag. Set to 1 when counting up and reset to 0 when counting down.
Bit 6 IDX:
Index. Set to 1 when selected index input is at active level.
Bit 7:
Not used is always 0.
