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ACCES I/O Products, Inc. 

MADE IN THE USA 

PCIe-ADIO16-16F Family Manual 

 

Rev B1 

In all other modes the FIFO Count reports the number of 

pairs

 of ADC Conversions are available in the FIFO.  Were you to read the data from the ADC FIFO (+30) you would read 

two 32-bit values per FIFO Count to gather the acquired data. However, in these modes it is generally best to let DMA transfer the FIFO data, which is performed at the native 
64-bit FIFO width. 

 

ADC FIFO Data, 30 of 32-bit Memory BAR[1]Read-Only 32-bits only 

bit  D31  

D30 

D29  D28  D27  D26  D25 

D24  D23  D22 through D20  D19  D18 through D16  D15 through D0 

Name  INVALID=1 

RUNNING  UNUSED 

 

0 (“VALID”)

  RSV 

DIO1  DIO0  RSV 

RSV 

TEMP  MUX  SEQ  Channel2:0 

Diff  Gain2:0 

ADC Counts (Two’s complement)

 

 

ADC FIFO Data:   Read the RAW-format ADC Conversion results (in twos-complement 16-bit form) and the associated status word. 

INVALID:  

If INVALID is SET then all other bits are undefined, and the entry should be discarded.  This can occur if you read from the ADC FIFO while the ADC FIFO Count 
(+28) is zero. 

RUNNING: 

SET indicates the ADC Sequencer is operating, taking either periodic (timer-driven) conversions or via the external ADC Start secondary digital function. 

DIO1:0: 

These bits indicate the state of the corresponding digital I/O pin at the time the paired ADC Conversion was sampled. 

TEMP: 

If TEMP is SET the ADC Counts are acquired from the ADAS3022’s onboard temperature sensor rather than from an analog input ch

annel.  Refer to ADC Control 

(+38) for more information about acquiring the temperature data. 

MUX:  

If MUX is SET the ADC Counts are acquired from the ADAS3022’s Auxiliary Mux inputs rather than from the normal Analog Input C

hannels.  Note, the PCIe-

ADIO16-16F does not have anything usefully connected to the Aux Mux inputs and you should not bother acquiring data from them. 

SEQ: 

The SEQ bit indicates which ADC the data is from, and can be thought of as Channel:3.  That is, if SEQ is set add +8 to the channel reported by the Channel2:0 
bits. 

Channel2:0: 

The 3 Channel bits indicate from which Analog Input the paired ADC Counts were sampled.  Refer to ADC Control (+38) for important information about the 
Channel bits re Differential operation. 

Diff: 

SET indicates the paired ADC Counts were sampled in Differential mode.  Refer to ADC Control (+38) for important information about the Channel bits re 
Differential operation. 

Gain2:0: 

The 3 Gain bits indicate at what gain code the paired ADC Counts were sampled.  Refer to the gain code table in ADC Advanced Sequencer Gain Control (+18) 
for how to interpret the Gain bits. 

ADC Counts: 

16-

bit two’s complement ADC counts, the ADC conversion result from the samples Channel at the specified Gain, sampled in Differe

ntial or Singled-ended / 

Pseudo-Differential mode as indicated by the Diff bit (D19). 

Please refer to the “Software Tips” section for details on how to translate RAW

-format ADC data into Volts 

 or skip the hassle and use our AIOAIO.dll API Library: 

 

ADC_GetImmediateV(iBoard, pVolts, iChannel, iRange);,  ADC_GetImmediateScanV(iBoard, pVolts[]); etc. 

 

ADC Control, 38 of 32-bit Memory BAR[1]Read/Write 32-bits only 

bit  D31 through D19 

D18 

D17 

D16  D15  D14 through D12 

D11 

D10  D9 through D7  D6 

D5 

D4 

D3 

D2 

D1 

D0 

Name  UNUSED 

SCAN 

CONFIG 

GO 

RSV 

IN

x

2:0 

COM 

RSV 

Gain2:0 

/MUX  SEQ1 

SEQ0 

/TEMP  RSV  CMS 

RSV 

Controls ADAS #0, channels 0-7 

The ADAS3022 is a very flexible ADC module and we highly recommend you use the AIOAIO.dll-provided API to avoid needing to know the following information. 

SCAN:   If SCAN is set (to 1) 

AND

 INx2:0 is non-

zero then each “ADC Start” event will acquire channels 0 through INx2:0 at the rate specified in +14.

 

CONFIG: If CONFIG is set then the ADC control bits (D15 through D0 of this register) will be written to the ADAS3022 

Содержание PCIE-ADIO16-16F

Страница 1: ...ESio com 10623 Roselle Street 800 326 1649 http accesio com PCIe ADIO16 16F San Diego CA 92121 1506 USA sales accesio com MADE IN THE USA 16 ANALOG INPUT 4 ANALOG OUTPUT 16 DIGITAL I O FOR PCI EXPRESS HARDWARE MANUAL MODELS PCIE ADIO16 16F FAMILY ...

Страница 2: ...art mode optimizes inter channel timing High impedance 8 channel input 1 MΩ 32k FIFO plus DMA for efficient robust data streaming 16 Digital I O pins with flexible secondary functions Four 16 bit analog outputs 5 per channel programmable ranges 0V to 5V 0V to 10V 2 5V 5V 10V Optional 4 20mA outputs Outputs Drive 10mA Guaranteed Onboard Watchdog with status output RoHS compliant standard CHAPTER 3 ...

Страница 3: ...8 9 43 ADC IN 9 ADC IN 10 11 45 ADC IN 11 ADC IN 12 13 47 ADC IN 13 ADC IN 14 15 49 ADC IN 15 ADC1 COMMON 17 51 ADC2 COMMON DAC 0 19 53 DAC2 DAC 1 21 55 DAC 3 Digital Ground 23 57 Digital Ground Digital Ground 24 58 Digital Ground DIO BitIndex 14 25 59 DIO BitIndex 15 Group 1 DIO BitIndex 12 26 60 DIO BitIndex 13 DIO BitIndex 10 27 61 DIO BitIndex 11 DIO BitIndex 8 28 62 DIO BitIndex 9 DIO BitInde...

Страница 4: ... CH0 1 0 Advanced Sequence Acquires Channel 0 using the gain selected via 18 bits 2 0 Conversion starts will automatically cycle through the channels from CH0 through INx2 0 and each channel is acquired at the per channel gain set in 18 The sequence repeats starting at CH0 after INx2 0 is acquired 1 1 Basic Sequence Acquires channel 0 using the gain set in Gain2 0 Conversion starts will automatica...

Страница 5: ...nd Feature Reset command bits and ADC Power Down control bit and status 4 W DAC Control DAC LTC2664 Command Register bits 8 R DAC 4 20mA mode Indicates which DACs if any have current output circuit installed C R ADC Base Clock Frequency of the ADC Sequencer Base Clock Hz used to calculate the ADC Rate Divisor for desired conversion rates 10 W R ADC Rate Divisor ADC Start Rate ADC Base Clock ADC Ra...

Страница 6: ...he LTC2664 Data Sheet for details Consult the AIOAIO Software Reference or our sample programs source to avoid the hassle DAC_SetRange1 iBoard iChannel iRange DAC_OutputV iBoard iChannel double Voltage DAC 4 20mA mode Offset 8 of 32 bit Memory BAR 1 Read 32 bits only bit D31 through D4 D3 D2 D1 D0 Name UNUSED DAC3 current mode only DAC2 current mode only DAC1 current mode only DAC0 current mode on...

Страница 7: ...V to IN or ADC COMMON results in 2 V span reversing the voltage polarity results in another 2 V span for a total Peak to Peak measurement capability of 4 V p p ADC Advanced Sequencer Gain Control 2 Offset 1C of 32 bit Memory BAR 1 Read Write 32 bits only bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSV AIN 15 GAIN2 0...

Страница 8: ... inputs and you should not bother acquiring data from them SEQ The SEQ bit indicates which ADC the data is from and can be thought of as Channel 3 That is if SEQ is set add 8 to the channel reported by the Channel2 0 bits Channel2 0 The 3 Channel bits indicate from which Analog Input the paired ADC Counts were sampled Refer to ADC Control 38 for important information about the Channel bits re Diff...

Страница 9: ...Name UNUSED RSV CONFIG RSV RSV INx2 0 COM RSV Gain2 0 MUX SEQ1 SEQ0 TEMP RSV CMS RSV Controls ADAS 1 channels 8 15 Refer to 38 ADC Control 1 for details IRQ Enable Clear and Status Offset 40 of 64 bit Memory BAR 2 3 Read Write 32 bits only bit D31 D30 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WDG UNUSED EXT1 EXT0 LDAC FOF FAF DTO DDONE ADCSTART ADCTRIG UNUSED e...

Страница 10: ...d optionally generate an IRQ enTRIG SET enTRIG to enable the ADC Trigger Digital Input Secondary Function on DIO15 so the selected edge will trigger timed ADC conversions and optionally generate an IRQ Consult the Software Tips section for details on using ADC Trigger Each Digital Input Secondary function has a configurable active edge rising or falling SET the corresponding edgeXXX bit to select ...

Страница 11: ...ch must transition to the kernel in order to perform any hardware operation This transition adds quite a lot of latency which varies between different OSes motherboards and revisions thereof etcetera A Windows XP system can see an additional 7µs per transaction a modern computer might see 3µs or less Any transaction from the kernel itself however avoids this additional overhead Real time operating...

Страница 12: ...et all applicable EM interference and emission standards However as they are intended for use installed on motherboards and inside the chassis of industrial PCs important care in the selection of PC and chassis is important to achieve compliance for the computer as a whole UL TUV Neither DC voltages above 3 3V nor AC voltages of any kind are consumed or produced during normal operation of this dev...

Страница 13: ... and invoiced COVERAGE FIRST THREE YEARS Returned unit part will be repaired and or replaced at ACCES option with no charge for labor or parts not excluded by warranty Warranty commences with equipment shipment FOLLOWING YEARS Throughout your equipment s lifetime ACCES stands ready to provide on site or in plant service at reasonable rates similar to those of other manufacturers in the industry EQ...

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