Manual PCI-DIO-48JP/JPS
16
To set outputs high (1) at Port B and the lower nybble of Port C:
50OUT B1,&HFF'Turn on all Port B bits
60OUT B2,&HF'Turn on all bits of Port C
lower nybble
ENABLING/DISABLING I/O BUFFERS
When using the tristate mode (Jumper in the TST position), the method to disable the I/O buffers involved
writing a control word to the Control Register at Base A3 and Base A7. This control word
was required to have bit D7 (the most significant bit) set. That meant that the PPI translated it as an “active
mode set” and reset the output data latches to “zero” on all output ports
and
the output buffers were
disabled. However, if the buffers are to be enabled at a later time, the output latches will be in a “zero”
state. For example, if all the outputs were 1's, they will now be 0's and the output buffers will be disabled.
This can be resolved as follows.
Two computer I/O bus addresses are available that permit you to enable or disable the I/O buffers at will,
without
programming the PPI mode
. Buffers for Port 0 bits are enabled/disabled at Base A8 and
buffers for Port 1 bits are enabled/disabled at Base A9. To enable the buffers and to set outputs to
the desired state, you can write to the Control Register with bit D7 low. If you wish to subsequently disable
the buffers, you can write to the Control Register with bit D7 high. In this way you can enable/disable the
output buffers without programming the PPI mode.
Note When writing a command byte to these cards while the TST jumper is installed, the PPI output
buffers are disabled. Thus, when you desire to to change the mode, you must first set the new mode and
then enable the buffers. Enabling the buffers can be done at either Base A3 (or +7) or Base
A8 (or +9).
CHANGE-OF-STATE INTERRUPTS
(Model 48JPS only)
At power-up or Reset, a register that enables change-of-state interrupts is set to zero. This
enables all
inputs to generate change-of-state interrupts.
During initialization this register should be programmed to
prevent interrupt generation by inputs that you do not want to cause change-of-state interrupts or by ports
that are programmed as outputs. To program this Change-of-State-Interrupt-Enable Register, write to it at
Base B. Data bits D0 through D5 control ports A, B, and C of the 8255 PPIs as shown in Table 4.
Bit Port
Controlled
D0
D1
D2
D3
D4
D5
Group 0, Port A
Group 0, Port B
Group 0, Port C
Group 1, Port A
Group 1, Port B
Group 1, Port C
Table 6-4: Change-of-State Interrupt Enable Register
Writing a “one” disables the port; writing a “zero” enables it. This register is latched. To clear the latch, write
anything at Base F.
