Manual PCI-A12-16A
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I/O location is accessed. The counter status byte provides information about the current output state of the
selected counter and its configuration. The status byte returned if STA=0 is:
B7 B6 B5 B4 B3 B2 B1 B0
OUT NC RW1 RW2 M2
M1 M0 BCD
OUT:
Current state of counter output pin.
NC:
Null count. This indicates when the last count loaded into the counter register has
actually been loaded into the counter itself. The exact time of load depends on the
configuration selected. Until the count is loaded into the counter itself, it cannot be
read.
RW1 & RW0:
Read/Write command.
M2, M1, M0:
Counter mode.
BCD:
BCD = 0 is binary mode, otherwise counter is in BCD mode.
If both STA and CNT bits in the counter status byte are set low and the RW1 and RW0 bits have both been
previously set high in the counter control register (thus selecting two-byte reads), then reading a selected
counter address location will yield:
1st Read:
Status byte
2nd Read:
Low byte of latched data
3rd Read:
High byte of latched data
After any latching operation of a counter, the contents of its hold register must be read before any subsequent
latches of that counter will have any effect. If a status latch command is issued before the hold register is
read, then the first read will read the status, not the latched value. In this case, the latched value may be read
after reading the status.
