127
MC96F8204
ABOV Semiconductor Co., Ltd.
11.8.8.3
UART Parity Generator
The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USTP1=1),
the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
11.8.8.4
UART Disabling Transmitter
Disabling the transmitter by clearing the TXE bit will not become effective until on going transmission is completed.
When the Transmitter is disabled, the TXD pin can be used as a normal general purpose I/O (GPIO).
11.8.9 UART Receiver
The USART receiver is enabled by setting the RXE bit in the USTCR2 register. When the receiver is enabled, the RXD
pin should be set to RXD function for the serial input pin of UART by P0FSRL. The baud-rate, mode of operation and
frame format must be set before serial reception. In synchronous or SPI operation mode the SCK pin is used as
transfer clock input, so it should be selected to do SCK function by P0FSRH. In SPI operation mode the SS input pin
in slave mode or can be configured as SS output pin in master mode. This can be done by setting USTSSEN bit in
USTCR3 register.
11.8.9.1
UART Receiving RX data
When UART is in synchronous or asynchronous operation mode, the receiver starts data reception when it detects a
valid start bit (LOW) on RXD pin. Each bit after start bit is sampled at pre-defined baud-rate (asynchronous) or
sampling edge of SCK (synchronous), and shifted into the receive shift register until the first stop bit of a frame is
received. Even if there’s the second stop bit in the frame, the second stop bit is ignored by the receiver. That is,
receiving the first stop bit means that a complete serial frame is presented in the receiver shift register and contents of
the shift register are to be moved into the receive buffer. The receive buffer is read by reading the USTDR register.
If 9-bit characters are used (USTS
[2:0] = “111”), the ninth bit is stored in the USTRX8 bit position in the USTCR3
register. The nineth bit must be read from the USTRX8 bit before reading the low 8 bits from the USTDR register.
Likewise, the error flags FE, DOR, PE must be read before reading the data from USTDR register. It
’s because the
error flags are stored in the same FIFO position of the receive buffer.
Содержание MC96F8204 Series
Страница 13: ...13 MC96F8204 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 20 Pin SOP Package...
Страница 14: ...14 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 2 20 Pin TSSOP Package...
Страница 15: ...15 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 3 16 Pin SOPN Package...
Страница 16: ...16 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 4 10 Pin SSOP Package...
Страница 17: ...17 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 5 8 Pin SOP Package...
