12. Timer 0/1/2/3/4/5
A96G140/A96G148/A96A148 User’s manual
112
The timer/counter 2 can be a divided clock of a system clock which is selected from prescaler output
and T1 A Match (timer 1 A match signal). The clock source is selected by a clock selection logic,
controlled by clock selection bits (T2CK[2:0]).
TIMER 2 clock source: fX/1, fX/2, fX/4,fX/8,fX/32, fX/128, fX/512 and T1 A Match
In capture mode, data is captured into input capture data registers (T2BDRH/T2BDRL) by EINT12. In
timer/counter mode, whenever counter value is equal to T2ADRH/L, T2O port toggles. In addition, the
timer 2 outputs PWM waveform to PWM2O port in the PPG mode.
Table 18. TIMER 2 Operating Modes
T2EN
P1FSRL[3:2]
T2MS[1:0]
T2CK[2:0]
Timer 2
1
11
00
XXX
16 Bit Timer/Counter Mode
1
00
01
XXX
16 Bit Capture Mode
1
11
10
XXX
16 Bit PPG Mode(one-shot mode)
1
11
11
XXX
16 Bit PPG Mode(repeat mode)
12.3.1
16-bit timer/counter mode
16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter
registers and data registers as shown in figure 44. The counter register is increased by internal or timer
1 A match clock input.
Timer 2 can use the input clock with one of 1, 2, 4, 8, 32, 128, 512 and T1 A Match prescaler division
rates (T2CK[2:0]). When the values of T2CNTH/T2CNTL and T2ADRH/T2ADRL are identical to each
other in timer 2, a match signal is generated and the interrupt of Timer 2 occurs. The T2CNTH/T2CNTL
values are automatically cleared by the match signal. It can be cleared by software (T2CC) too.
