3-10 Chapter
3
HyperTransport Config
This item configures width and frequency for HyperTransport. Click <Enter> key to
enter its submenu:
CPU1/CPU2 LDT Bus Width
This item specifies CPU1 to CPU2 Hyper Transport Link Data width.
CPU1/CPU2 LDT Bus Freq.
This item specifies CPU1 to CPU2 Hyper Transport Link Clock frequency.
CPU1/PCI-X Bridge Width
This item specifies CPU1 to PCI-X Hyper Transport Link Data width.
CPU1/PCI-X Bridge Freq.
This item specifies CPU1 to PCI-X Hyper Transport Link Clock frequency.
PCI-X/South Bridge Width
This item specifies PCI-X to South Bridge Hyper Transport Link Data width.
PCI-X/South Bridge Freq.
This item specifies PCI-X to South Bridge Hyper Transport Link Clock frequency.
SU-2S
Содержание SU-2S
Страница 1: ...SU 2S Dual Opteron Server Board Socket 940 User s Manual Rev 1 00...
Страница 7: ...Introduction 1 3 1 2 Layout Diagram User s Manual...
Страница 16: ...2 8 Chapter 2 2 3 5 PCI Slots PCI1 PCI5 PCI1 PCI3 PCI X 64bit 100MHz PCI4 PCI5 PCI 32bit 33MHz SU 2S...
Страница 24: ...2 16 Chapter 2 2 3 13 Low Pin Count Connection Header LPC Reserved for internal testing SU 2S...
Страница 28: ...2 20 Chapter 2 2 20 Chapter 2 SU 2S SU 2S...