Abit Fatal1ty AN8 SLI, Руководство пользователя

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3-16 Chapter 3
DRAM Timing Selectable:
This item selects the DRAM timing mode. When set to “ By SPD ”, the BIOS will read the DRAM module
SPD data and automatically set to the values stored in it. Leave this item to its default “ Auto ” setting.
! DRAM Clock:
This item sets the DRAM clock of your DRAM module. The system may be unstable or unable to boot up
if your DRAM module does not support the clock you set.
When set to [By SPD], the BIOS will read the DRAM module SPD data and automatically set the DRAM
clock by the value stored in it.
! CAS Latency Time:
Three options are available: 2
$
2.5
$
3. The default setting is 2.5 . You can select SDRAM CAS
( C olumn A ddress S trobe) latency time according your SDRAM specification.
! Row Cycle Time:
This item specifies the RAS# active to RAS# active time or auto refresh time of the same bank.
! Row Refresh Cycle Time:
This item specifies the auto refresh active to RAS# active time or RAS# auto refresh time.
! RAS# to CAS# Delay:
This item specifies the RAS# active to CAS# read write delay time to the same bank.
! RAS# to RAS# Delay:
This item specifies the RAS# active to RAS# active delay time of different bank.
! Min. RAS# Active Time:
This item specifies the minimum RAS# active time.
! RAS# Precharge Time:
This item specifies the RAS# precharge time.
! Write Recovery Time:
This item specifies the time measured from the last write datum is safely registered by the DRAM.
! Write to Read Delay:
This item specifies the time measured from the rising edge following the last non-masked data strobe to
the rising edge of the next read command.
! DRAM Command Rate:
Two options are available: 2T Command or 1T Command. The default setting is 2T Command . When the
host (northbridge) locates the desired memory address, it then processes the wait state of commands.
! Burst Length
DDR SDRAM modules provide a Burst mode that means an auto precharge function for programmable
READ or WRITE burst lengths of 4 or 8 locations.
This means that if we set burst length to 8, the address bus will access 8 bytes each cycle to precharge,
etc.
Fatal1ty AN8 SLI