Abit AN8 32X, Руководство пользователя

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BIOS Setup 3-15
DRAM Configuration:
Click <Enter> key to enter its submenu:
Phoenix – Award BIOS CMOS Setup Utility
DRAM Configuration
DRAM Timing Selectable Auto Item Help
X - DRAM Clock Auto
X - CAS Latency Time Auto
X - Row Cycle Time Auto
X - Row Refresh Cycle Time Auto
X - Min RAS# Active Time Auto
X - RAS# to CAS# Delay Auto
X - RAS# Precharge Time Auto
X - RAS# to RAS# Delay Auto
X - Write Recovery Time Auto
X - Write to Read Delay Auto
X - Read to Write Delay Auto
X - DRAM Command Rate Auto
X - Bank Interleaving Enabled
X - Burst Length 4 beats
MTRR mapping mode Continuous
32 bit Dram Memory Hole Auto
↑↓→←
:Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
DRAM Timing Selectable:
This item selects the DRAM timing mode. When set to “
By SPD
”, the BIOS will read the DRAM module
SPD data and automatically set to the values stored in it. Leave this item to its default “ Auto ” setting.
DRAM Clock:
This item sets the DRAM clock of your DRAM module. The system may be unstable or unable to boot up
if your DRAM module does not support the clock you set.
When set to [By SPD], the BIOS will read the DRAM module SPD data and automatically set the DRAM
clock by the value stored in it.
CAS Latency Time:
You can select SDRAM CAS ( C olumn A ddress S trobe) latency time according your SDRAM
specification.
Row Cycle Time:
This item specifies the RAS# active to RAS# active time or auto refresh time of the same bank.
Row Refresh Cycle Time:
This item specifies the auto refresh active to RAS# active time or RAS# auto refresh time.
Min. RAS# Active Time:
This item specifies the minimum RAS# active time.
RAS# to CAS# Delay:
This item specifies the RAS# active to CAS# read write delay time to the same bank.
User’s Manual