30 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board
Publication No. 500-001184-000 Rev. B.0
3.1.1 Board ID (BD ID) Register
3.2 Control and Status Registers
3.2.1 CSR1 Bit Definitions
The Offset for the Control and Status Register is $XXXX02.
Bit 15:
Fail LED
- Writing a one (1) to this bit will turn off the LED. Writing a zero (0)
to this bit will turn on the LED.
Default is 0
.
Bit 14:
Counter Reverse
- Writing a one (1) to this will reverse the direction of the
counter. Given a counter input, if the counter increment, it now decrements
and visa versa. This applies to all 4 modes.
Default is 0 for normal direction
.
Bit 13:
Data FIFO Empty
– This bit is a read-only flag that when set, indicates that
the COS/SOE FIFO is empty.
Bit 12:
Data FIFO Full
– This bit is a read-only flag that when set, indicates that the
COS/SOE FIFO is full, and any additional COS/SOE events may be lost. An
interrupt is generated at the COS level and vector.
Bit 11:
COS/SOE (0/1)
- Change-of-State/Sequence-of-Events: Bit 11 is set to zero (0)
for the Change-of-State mode, and to a one (1) for the Sequence-of -Events
mode.
Default is 0
.
Bit 10:
ROFE/ROAK(0/1)
- Release interrupt on FIFO Empty/Release Interrupt on
Acknowledge.
Default is 0
.
Bit 09:
EN CTR FIFO
- Bit 9 enables storage of the Counter value each time a COS, or
SOE event occurs.
Default is 0
.
$24
CH_INT_ENA
Channel Interrupt Enable register
RW
$28
DB_Data
Debounced Data Register
R
$30
FREV
Firmware Revision ID
R
$34
CSR2
Control and Status Register #2
RW
Table 3-1 VMIVME-1184 Address Map (Continued)
Relative Address
Register Name
Register Function
R/RW
Table 3-2 Board ID Register Bit Map
BD ID: Offset $XXXX
00
(fixed @ $6700)
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
0
1
1
0
0
1
1
1
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0
0
0
0
0
0
0
0
Table 3-3 Control and Status Register 1 Bit Map
CSR1: Offset $XXXX
02
(fixed @ $6700)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 09
Bit 08
Fail LED
Counter Reverse FIFO Empty
FIFO Full
COS/SOE
(0/1)
ROFE/ROAK
(0/1)
EN CTR FIFO Extend
Debounce
Bit 07
Bit 06
Bit 05
Bit 04
Bit 03
Bit 02
Bit 01
Bit 00
Debounce Time
Channel Enable Double Count CTR_FIFO_Full CTR_FIFO_Empty MRK_Reset
CTR_ENA
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