Publication No. 500-001184-000 Rev. B.0
Theory of Operation 17
During this test, two channels are actually changing value after State 1. In State 2,
channel 0 has changed from a 1 to a 0, and channel 1 has changed from a 0 to a 1.
Theoretically, these changes are simultaneous, and are viewed as a single COS
event. The following, factors can be introduced to make the arrival of signals on
different channels non-simultaneous:
• Comparators and Opto Couplers have different times on rising vs. falling
edges.
• Traces, both inside and outside of FPGAs, can have slightly different lengths.
• Cables between sensors and I/O boards may not have precisely matched
lengths.
If any of the above conditions occur, then data transmitted simultaneously on
two or more channels may not arrive simultaneously at the COS detection
circuitry.
The need for the COS inputs to be synchronized to a common clock also
aggravates this situation. If two incoming signals arrive as little as 2 nanoseconds
apart, the first signal may arrive prior to the synchronizing rising clock edge, and
the second signal may arrive after the rising clock edge. If this occurs, the skew
between the two signals is stretched to the period of the 16 MHz synchronizing
clock. The debounce circuitry is another factor that can skew simultaneous events.
Consider a situation where two incoming signals are skewed by one or more
synchronizing clock cycles, the synchronized incoming signals can encounter
another early-late condition (as was in the synchronizing clock) with the
debounce circuitry. With the COS detection and FIFO circuitry running at the
VMEbus clock rate, the first arriving signal will have been stored by the COS
circuit, in the COS FIFO before the second arriving signal has passed the
debounce circuitry. If the second signal is also flagged, the two COS events would
be stored in the COS FIFO instead of one. This “double-hit” COS event can show
what appears to be an invalid state condition.
Consider the following example:
1. Set Channel 5 for rising edge events and channel 4 to falling edge
2. Set the CSR to see SOE mode, the expected FIFO output is:
The actual FIFO output, due to skew introduced by cabling, synchronizing clock
skewing, and/or debounce skewing, may appear as follows:
Channel 5
Channel 4
Previous State 1
0
1
01 to 10 change occurs here
COS State 1
1
0
Channel 5
Channel 4
Previous State 1
0
1
01 to 10 change occurs here, but Channel 4 lags Channel 5 by 3nsec
(New data appears on Channel 5, but old data still lingers on Channel 4)
COS State 1
1
1
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