68 PCIE-5565RC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts
Publication No. 500-9300875565-000 Rev. C.0
setting the Remap Value to 0 at the beginning of the installed memory address
space. This gives the user application PIO access to the Reflective Memory
locations $00000000 up to $001FFFFF. The user application can set the Local Base
Address (Remap) register pointing to any valid window in the installed memory.
For example, the user application can write $00200000 to the Remap register to
access the second 2 MByte PCI PIO window. The register value will be $00200001
since bit-0 is hardwired to 1. This gives the user application PIO access to the
Reflective Memory locations $00200000 up to $003FFFFF. The user application
uses the same PCIBAR3 window ranging from $F7600000 up to $F77FFFFF.
NOTE
After writing a new value to the LAS1BA remap register, the user application should read the LAS1BA
remap register before accessing the new window. This ensures the new window mapping has taken
effect and subsequent memory accesses will be to the new memory window.
In summary, register LAS1RR is the range register corresponding to the size of the
PCI window and is read-only. Register LAS1BA is the writeable base address
register. It is used to remap or offset the PCI PIO window to access other sections
of the installed memory. The RFM-5565 firmware prevents the user from entering
an invalid Remap Value. The value written must be a multiple of the PCI window
size. For example, using a PCI window size of 2 MByte with 64 MByte of installed
memory means there are 32 valid base address settings from $00000000 to
$03E00000, incrementing by $00200000 (all other bits are masked off when
written). Also, a 64 MByte card with a 64 MByte window has no valid base
address settings other than the default 0.
Since the PCI window size and the Remap register only affect PCI PIO accesses,
DMA (Local-to-PCI and PCI-to-Local) can be used normally to transfer up to
$7FFFFF bytes with another location on the PCI bus regardless of the Remap
value.
3.7 Example of Network Interrupt Handling
The following is an example of the steps necessary to set up the RFM-5565 to
generate a PCI interrupt in response to one of the four basic network interrupts.
This example also lists the steps necessary to service that interrupt. When using
this example, it is advisable to examine
Figure 2-1
on page 29 and
Figure 3-1
on
page 63 to obtain a visual sense of the circuitry involved.
3.7.1 Setup
1. Clear any prior unscheduled interrupts in the SID1 FIFO by writing zero (0)
to the SID1 at P offset $24.
2. Clear any prior unscheduled interrupts in the SID2 FIFO by writing zero (0)
to the SID2 at P offset $2C.
3. Clear any prior unscheduled interrupts in the SID3 FIFO by writing zero (0)
to the SID3 at P offset $34.
4. Clear any prior unscheduled interrupts in the SID4 FIFO by writing zero (0)
to the SID4 at P offset $3C.
5. Using a read-modify-write operation, set Bit 07, Bit 02, Bit 01 and Bit 00 high
(1) in the LIER register at P offset $14. This allows any one of the
four basic network interrupts to assert the onboard signal LINTi#, provided
the global enable in the LISR is also high (1).
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