Publication No. 500-657055-000 Rev. G
Overview 13
acquisition systems and anywhere that the highest performance processing
power in a single CompactPCI chassis slot is desired.
PowerPC RISC Microprocessor
The microprocessor used on the VMICPCI-7055/CPCI-7055RC is a 32-bit
PowerPC 750GX architecture in a 0.13 micron CMOS technology with six levels of
copper interconnect. The performance enhancements included in the
microprocessor are:
• Onboard L2 cache with locking by way (1 MByte)
• L1 data cache availability
• Bus pipelining (consecutive data reads)
• Additional floating point unit (FPU) reservation station and improved
reciprocal estimates
L1 Data Cache
The 750GX L1 data cache supports miss-under-miss access, meaning that with
one miss outstanding, the cache can continue to be accessed until a second miss
occurs. In previous PowerPC 750 microprocessor implementations the data bus
width for bus interface unit (BIU) accesses of the L1 data cache array was 64 bits.
To cast out or to reload a 256-bit cache line required four access cycles. On the
750GX, this bus has been expanded to 256 bits. As a result, cache line data bursts
can be read from or written to the cache array in a single cycle, reducing cache
contention between the BIU and the load-store unit.
L2 Cache
The 750GX processor is available with 1 MByte of L2 cache. The cache is two-way
set associative; each way contains 4096 blocks and each block consists of two 32-
byte sectors. Array read and write operations execute in one processor cycle.
Writes to the array are 64 bits wide, while reads are 256 bits wide.
In addition, the L2 cache has an 8-bit ECC for every 64-bit word in memory that
can be used to correct a majority of single bit errors and detect multiple bit errors.
The L2 tags also support parity and locking by way.
Bus Pipelining
The 60x bus has decoupled address and data buses, allowing transactions to be
pipelined on the bus. That is, the address operation for a second transaction can
be initiated before the data operation for a previous transaction is complete. The
750GX BIU allows pipelined read transactions to a depth of two back-to-back
reads.
