abaco systems XVR16 Series, Справочник по аппаратуре, Страница: 92 / 151

92 XVR16*4th Generation Intel® Core™ i7 Based Rugged VME Single Board Computer Publication No. 500-9300007876-000 Rev. C.0
Table 8-23 Timer 1 Control and Status Register 1 (CSR1) (0x658)
Bit R/W Description Reserved
7 R Timer IRQ status
1 = Pending
0 = No Interrupt
NA
6 R Reserved 0
5:4 R/W Clock source select:
00 = Use 2 MHz FPGA Clock (default)
01 = Reserved
10 = Reserved
11 = Reserved
0
3 R/W Timer Read selection
1 = Read Timer Load value
0 = Read Current Time value
0
2:1 R/W Clock divider (Value when 2 MHz Clock Used)
00 = 1:1 (2 MHz)
01 = 1:2 (1 MHz)
10 = 1:4 (500 KHz)
11 = 1:8 (250 KHz)
0
0 R/W Enable Timer IRQ
1 = IRQ Enabled
0= IRQ Masked
0
Table 8-24 Timer 1 Control and Status Register 2 (CSR2) (0x659)
Bit R/W Description Default
7:5 R Reserved 0
4 R/W Timer Read Latch Select
1 = Latch All Timers on read of Timer 0 LSB
0 = Latch Individual Timers on the read of individual
Timer LSB
Note: Setting this bit in any timer CSR2 register will
have the same effect of latching ALL timers on read of
timer 0 LSB
0
3:2 R Reserved 0
1 R/W Timer On-Shot Enable
1 = Timer will count down once and stop
0 = Timer will count down and reload at terminal count
0
0 R/W Timer Enable
1 = Timer enabled
0 = Timer disabled
0