42 V7768/V7769* Intel® Core™ Duo Processor VME Single Board Computer
Publication No: 500-9300007768-000 Rev. H.0
2.5.2 PCI Interrupts
The PMC PCI-X sites of the V7769 connect Standard PCI Interrupt Lines to the
PCI-E to PCI-X bridge as shown in
on page 44. The PCI-E bridge (PLX
PEX8114) converts the PCI INTx interrupts into virtual PCI Express interrupts
that are signaled back to the chipset over the PCI Express Interface.
Interrupts on Peripheral Component Interconnect (PCI) Local Bus are defined as
“level sensitive,” asserted low (negative true), using open drain output drivers.
The assertion and de-assertion of an interrupt line, INTx#, is asynchronous. A
device asserts its INTx# line when requesting attention from its device driver.
Once the INTx# signal is asserted, it remains asserted until the device driver clears
the pending request. When the request is cleared, the device de-asserts its INTx#
signal.
PCI defines one interrupt line for a single function device and up to four interrupt
lines for a multifunction device or connector. For a single function device, only
INTA# may be used while the other three interrupt lines have no meaning.
on page 44 depicts the V7768/V7769 interrupt logic pertaining to
FPGA timer
operations and the PCI expansion site.
Any function on a multifunction device can be connected to any of the INTx#
lines. The Interrupt Pin register defines which INTx# line the function uses to
request an interrupt. If a device implements a single INTx# line, it is called INTA#;
if it implements two lines, they are called INTA# and INTB#; and so forth. For a
multifunction device, all functions may use the same INTx# line, or each may
have its own (up to a maximum of four functions), or any combination thereof. A
single function can never generate an interrupt request on more than one INTx#
line.
The PIC accepts the PCI interrupts through lines that are defined by the BIOS.
