Chapter 3 BIOS setup
57
System BIOS Cacheable
Disabled
Enabled
Video BIOS Cacheable
Disabled
Enabled
Memory Hole At 15M-16M
Disabled
Enabled
CPU Latency Timer
Enabled
Disabled
Delayed Transaction Enabled
Disabled
AGP Graphics Aperture Size 64MB
32MB
Display Cache Frequency 100MHz
133MHz
System Memory Frequency Auto
100MHz
133MHz
On-Chip Video Window Size 64MB
Disabled
CAS# Latecy 3
2
Paging Mode Control Open
Close
RAS-to-CAS Override By CAS# LT
Override (2)
RAS# Timing Fast
Slow
RAS# Precharge Timing Fast
Slow
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle.
Содержание PCM-6896
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Страница 19: ...1 0 PCM 6896 User Manual ...
Страница 29: ...2 0 PCM 6896 User Manual COM3 COM4 Selection JP2 JP3 12V 1 3 5 2 4 6 5V RI default 1 3 5 2 4 6 1 3 5 2 4 6 ...
Страница 53: ...4 4 PCM 6896 User Manual ...
Страница 54: ...C H A P T E R 3 BIOS Setup This chapter describes how to set BIOS configuration data ...
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Страница 101: ...Appendix A Watchdog Timer 93 A P P E N D I X WatchDog Timer A ...