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FMC150 User Manual

r1.6

FMC150

User Manual

4DSP LLC, USA

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This document is the property of 4DSP LLC and may not be copied nor communicated to a
third party without the written permission of 4DSP Inc.

© 4DSP LLC 2010

Содержание FMC150

Страница 1: ...l r1 6 FMC150 User Manual 4DSP LLC USA Email support 4dsp com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP I...

Страница 2: ...date oscillator details in the clock tree description Removed DIP switch definition 1 1 2010 10 21 Changed order code scheme 1 2 2010 11 15 Correction in block diagram 1 3 2011 01 14 Correction of sec...

Страница 3: ...acteristics 9 4 4 Analog input channels 10 4 5 Analog output channels 11 4 6 External trigger input 11 4 7 Clock tree 11 4 7 1 External clock input 11 4 7 2 Architecture 11 4 7 3 PLL design 12 4 8 Pow...

Страница 4: ...FMC150 User Manual r1 6 FMC150 User Manual January 2012 www 4dsp com 4 10 Warranty 17 Appendix A LPC pin out 18...

Страница 5: ...GT Multi Gigabit Transceiver MSB Most Significant Bit s PCB Printed Circuit Board PCI Peripheral Component Interconnect PCIe PCI Express PLL Phase Locked Loop PMC PCI Mezzanine Card PSSR Power Supply...

Страница 6: ...channel 14 bit 250Msps ADC and TI s DAC3283 dual channel 16 bit 800Msps DAC The analog signal inputs are AC coupled connecting to MMCX SSMC coax connectors on the front panel The FMC150 allows flexibl...

Страница 7: ...rrier card compliant to the FMC standard The FMC carrier card must support the low pin count connector 160 pins The FMC carrier card may support the high pin count connector 400 pins The FMC carrier c...

Страница 8: ...nel From top to bottom analog in A analog in B clock in CLK trigger in TRG analog out C and analog out D Figure 3 Bezel design 4 2 Electrical specifications The FMC150 card is designed to operate in L...

Страница 9: ...e 14 have been taking into account resulting in the following arrangement The clock and data pairs from the ADC are mapped to LA00_CC and LA01 LA14 respectively The remaining connections from this ass...

Страница 10: ...tput Data width LVDS 7 pairs DDR per channel Data Format Offset binary or 2 s complement Sampling Frequency Range up to 250MHz DAC Input Data width LVDS 8 pairs DDR Data Format Offset binary or 2 s co...

Страница 11: ...ference clock input in case the internal clock is desired Note when internal clock is enabled and there is no need for an external reference it is highly recommended to leave the external clock input...

Страница 12: ...connects to the FMC connector to be used as reference clock for the D A clock and data signals CLK_TO_FPGA_P N 4 7 3 PLL design The PLL functionality of the CDCE72010 is used to operate from an intern...

Страница 13: ...d according to Table 4 Voltage Pins Max Amps Max Watt 3 3V 4 3 A 10 W 12V 2 1 A 12 W VADJ 1 8V 2 5V 4 4 A 10 W VIO_B VADJ 2 1 15 A 2 3 W Table 4 FMC standard power specification The power provided by...

Страница 14: ...t on the CDCE72010 when an external sampling clock is applied 5 In case internal clock is used the PLL functions needs to be enabled The recommended phase detector frequency is 160kHz In case the inte...

Страница 15: ...channel 4 to 7 3 It is recommended to power down the unused features DAC operation precision current source and reference buffer amplifier 4 Internal reference must be selected Since the AMC7823 is po...

Страница 16: ...the devices is within the allowed range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 6 3 2 Conduction cooling In demanding environments the ambient...

Страница 17: ...SSMC screw coupling 2 Analog Signal Input Standard Feature VCXO option 491 52MHz 1 VCXO option 737 28MHz 2 Custom VCXO option contact factory 3 Mil I 46058c Conformal Coating No Conformal Coating 1 Ad...

Страница 18: ...FMC150 User Manual r1 6 Appendix A LPC pin out Colors indicate _CC signal and associated I O signal groups as recommended by AV57 1 in Table 14...