UM027 FC6301 User Manual
r1.3
UM027
www.4dsp.com
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4.7 BLAST sites
Thanks to the availability of 3 BLAST sites a wide variety of memory and processing modules
can be connected to the Virtex-6 device. For each BLAST site it is possible to choose from
the list of available BLAST modules.
For more information about the available BLASTs on the FC6301 please consult the
following page: BLAST modules
http://www.4dsp.com/BLAST.htm
Due to its small form factor and ease of design, the BLAST modules enable a rapid solution
for custom memory or processing requirements.
BLAST SITE
1
2
3
4
Single BLAST
YES
YES
YES
YES
Single
Extended
BLAST
YES
YES
YES
YES
Double
BLAST
NO
NO
NO
NO
Double
Extended
BLAST
NO
NO
NO
NO
Table 9: BLAST Configuration Options
BLAST SITE
1
2
3
4
DDR3
YES
YES
YES
YES
DDR2
YES
YES
YES
YES
QDR
YES
YES
YES
YES
ADV212
JPEG2000
YES
YES
YES
YES
32GB NAND
FLASH
YES
YES
YES
YES
Table 10: BLAST Memory/Processing Options
4.8 Clock tree
The FC6301 clock architecture offers an efficient distribution of low jitter clocks. A 100 MHz
clock from a low jitter oscillator is distributed to the FPGA and the PCIexpress to PCI bridge
using a PCI express jitter attenuator (ICS847003). This clock is used as the PCIexpress
reference clock.
A low jitter programmable clock device (CDCE925) able to generate frequencies from
62.5MHz to 255.5MHz in steps of 0.5MHz is also available. This clock management
approach ensures maximum flexibility to efficiently implement multi-clock domains algorithms
and use the memory devices at different frequencies.
Further there is also a fixed 50 MHz clock is distributed to the FPGA and the CPLD.
