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User’s Guide

TPS7A21EVM-059 Evaluation Module

ABSTRACT

Figure 1-1. TPS7A21EVM-059 Evaluation Module

This user's guide describes the operational use of the TPS7A21EVM-059 evaluation module (EVM) as a 
reference design for engineering demonstration and evaluation of the TPS7A21 low-dropout linear regulator 
(LDO). Included in this user's guide are setup and operating instructions, thermal and layout guidelines, a 
printed-circuit board (PCB) layout, a schematic diagram, and a bill of materials (BOM).

Throughout this document, the terms 

evaluation board

evaluation module

, and 

EVM

 are synonymous with the 

TPS7A21EVM-059.

Table of Contents

1 Trademarks

..............................................................................................................................................................................

2

2 Introduction

.............................................................................................................................................................................

3

3 Setup

........................................................................................................................................................................................

3

3.1 LDO Input/Output Connector Descriptions.........................................................................................................................

3

3.2 Optional Load Transient Input/Output Connector Descriptions..........................................................................................

3

3.3 TPS7A21 LDO Operation...................................................................................................................................................

5

3.4 Optional Load Transient Circuit Operation.........................................................................................................................

6

4 Board Layout

...........................................................................................................................................................................

8

5 TPS7A21 EVM Schematic

....................................................................................................................................................

10

6 Bill of Materials

......................................................................................................................................................................

11

www.ti.com

Table of Contents

SBVU072 – OCTOBER 2021

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TPS7A21EVM-059 Evaluation Module

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Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for TPS7A21EVM-059

Page 1: ...t a schematic diagram and a bill of materials BOM Throughout this document the terms evaluation board evaluation module and EVM are synonymous with the TPS7A21EVM 059 Table of Contents 1 Trademarks 2 2 Introduction 3 3 Setup 3 3 1 LDO Input Output Connector Descriptions 3 3 2 Optional Load Transient Input Output Connector Descriptions 3 3 3 TPS7A21 LDO Operation 5 3 4 Optional Load Transient Circu...

Page 2: ...Layer Routing 8 Figure 4 3 Layer 2 8 Figure 4 4 Layer 3 8 Figure 4 5 Bottom Layer Routing 9 Figure 4 6 Bottom Assembly Layer and Silk Screen 9 Figure 5 1 Schematic 10 1 Trademarks LeCroy is a trademark of Teledyne LeCroy Kapton is a registered trademark of DuPont All trademarks are the property of their respective owners Trademarks www ti com 2 TPS7A21EVM 059 Evaluation Module SBVU072 OCTOBER 2021...

Page 3: ...N is a 3 pin header used to enable or disable the TPS7A21 The center pin of the 3 pin header is tied to the TPS7A21 EN input When the 2 pin shunt is placed across the top two pins of the header VIN is shorted to EN and the TPS7A21 is enabled When the 2 pin shunt is placed across the bottom two pins of the header GND is shorted to EN and the TPS7A21 is disabled Alternatively the 3 pin header can re...

Page 4: ...high frequency kelvin connection that allows accurate measurements of the load transient MOSFET gate to source voltage 3 2 8 TP2 and TP3 TP2 and TP3 allow the user to measure the gate drive resistance R8 when power is turned off to the EVM 3 2 9 TP4 TP4 is the enable pin to enable the gate driver device Tie this pin to GND to enable the gate driver Setup www ti com 4 TPS7A21EVM 059 Evaluation Modu...

Page 5: ...2 pin shunt across the header to tie VIN to EN to enable the device 2 Place a 2 pin shunt across the header to tie GND to EN or leave the 3 pin header floating to disable the device Alternatively by connecting an external function generator to TP1 EN and a nearby GND post J6 the user can enable or disable the TPS7A21 LDO after VIN is applied Figure 3 1 shows the result of the TPS7A21EVM 059 during...

Page 6: ...urrent probes a 10 AWG wire can be used WARNING The sensors of some current probes are tied to GND and cannot come into contact with energized conductors See the user manual of your current probe for details If your current probe has this limitation use a thin strip of electrical or Kapton tape to isolate the current sense path from the current probe Optional kelvin sense points are provided using...

Page 7: ...t Therefore use a load transient pulse duration limit of 1 ms to prevent excessive heating of the pulsed resistors R2 R3 R4 R5 and R6 Configure a function generator for the 50 Ω output in a 0 V DC to 5 V DC square pulse If necessary burst mode can be configured in the function generator for repetitive low duty cycle load transient testing A 3 4 kΩ resistor is installed on the EVM at R8 This resist...

Page 8: ... LDO LMG1020YFFR gate driver and pulsed resistors R2 R3 R4 R5 and R6 are most at risk of raising to a high junction temperature during normal operation Figure 4 1 Top Assembly Layer and Silk Screen Figure 4 2 Top Layer Routing Figure 4 3 Layer 2 Figure 4 4 Layer 3 Board Layout www ti com 8 TPS7A21EVM 059 Evaluation Module SBVU072 OCTOBER 2021 Submit Document Feedback Copyright 2021 Texas Instrumen...

Page 9: ...om Layer Routing Figure 4 6 Bottom Assembly Layer and Silk Screen www ti com Board Layout SBVU072 OCTOBER 2021 Submit Document Feedback TPS7A21EVM 059 Evaluation Module 9 Copyright 2021 Texas Instruments Incorporated ...

Page 10: ...H A2 OUTL B2 IN C2 GND B1 IN C1 LMG1020YFFR U2 1 2 3 4 5 J17 J14 VDD J18 GND 50V 10uF C12 50V 10uF C11 1 00k R1 EN B1 IN A1 GND B2 OUT A2 TPS7A2133PYWDJ U1 1 2 J10 50V 0 1uF C13 2 2µF 10V C2 10V 2 2uF C3 154 R5 154 R6 154 R4 154 R3 1 2 3 4 J11 GND EN VIN EN VOUT 154 R2 100V 1pF C9 0 R10 0 R7 3 5 6 8 4 7 1 2 Q1 CSD17313Q2 1 2 3 4 5 J19 1nF 100V C15 0 R11 J12 J13 1 2 3 4 5 J16 50V 0 015uF C10 49 9 R...

Page 11: ...30X40SMT Any J17 1 SMA Straight Jack Gold 50 Ohm TH SMA Straight Jack TH 901 144 8RFX Amphenol RF Q1 1 30V MOSFET N CH 30 V 5 A DQK0006C WSON 6 DQK0006C CSD17313Q2 Texas Instruments None R8 1 3 40k RES 3 40 k 1 0 125 W AEC Q200 Grade 0 0805 805 ERJ 6ENF3401V Panasonic R12 1 49 9 RES Thick Film 49 9Ω 1 0 75W 100ppm C 1206 1206 CRCW120649R9FK EAHP Vishay Dale SH J1 1 1x2 Shunt 100mil Gold plated Bla...

Page 12: ...F J6 J7 0 Terminal Block 5 mm 2x1 Tin TH Terminal Block 5 mm 2x1 TH 691 101 710 002 Wurth Elektronik J10 0 Header 100mil 2x1 Gold TH Sullins 100mil 1x2 230 mil above insulator PBC02SAAN Sullins Connector Solutions J11 0 Header 100mil 2x2 Gold TH 2x2 Header TSW 102 07 G D Samtec R1 R9 0 1 00k RES 1 00 k 1 0 125 W AEC Q200 Grade 0 0805 805 ERJ 6ENF1001V Panasonic R2 R3 R4 R5 R6 0 154 RES 154 1 0 5 W...

Page 13: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 14: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 15: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 16: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 17: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 18: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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