Sharp MZ1F10 Service Manual Download

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Summary of Contents for MZ1F10

Page 1: ... MZ 5600A 3 BASIC OPERATION 5 4 DRIVE INTERFACE 8 5 ENCODER DECODER DATA SEPARATOR 10 6 MAINTENANCE 12 7 EXPLANATION OF LSI 15 9 PARTS GUIDE AND LIST ...

Page 2: ...red to RAM by DMA of NDC 840 Status and Data Read are set by DMA in the register of NDC848 and are read by the host 2 1 Main Operation Time Chart 1 COMMAND SET 1 0pon 11 r 0383JH I ___ _J IOWC DATA CS ADI 0 ADRI DRQ H IJoVR UOO UU7 J n Jr c c 1 c J note host signals internal signals 1 MZ 5600A 2 STATUS READ 1 0 port H I 0380 HL _____ J DATA H L H DDO DD7 _ ___ z J 25 ns I 0 31 J 1 25 ns oin 1 oin ...

Page 3: ...ost side is slower than that of the disk it can be transferred With multisector mode transfers a 1 sector interval transfer can be executed at different transfer rates from the host lt can be transferred if the DMA transfer rate is slower than that of the disk The host s burden is reduced The host s cycle steal and high priority process can interrupt With multisector mode process dificiency does n...

Page 4: ...2 Magnification of the A Part MZ 5600A _____ ______ nL ___ ___ L_ I I I I I I I I I 3 Data Read NDC848 17 CS NDC848 18 DRD NDC848 19 DWI NDC848 16 HADR 1 I I I I I I I I 1000 2000 I I rl l I I I I I I I I I I I I I NDC848 15 HADRO DRQ NDC848 14 I NTR 4 Magnification of the B Part 0 ____J 3 0246 I 0271 0296 I I I I I I TI I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 5: ... unit address etc 4 2 4 1 Timing 1 Format INDEX AM ENABLEO I AM FOUND READ GATE 3 READ DATA 4 WRITE GATES WRITE DATA 6 2 Magnificaiton of the A Part 2 a 0169 Q 0419 0669 I I I I I I I I T I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 5 6 7 3 Magnification of the 8 Part o nL_________________ L__ Ill 2 3 nll 0480 Q 0700 0980 I I I I I I I I I I I I I I I I I I I I...

Page 6: ...ead Operation MZ 5600A In the read operation the ID read is first executed to find the designated sector On finding the desired ID field data are read The data read by the disk are separated NRZ Data and Clock from MFM Data are transferred to NDC 840 The data are converted from serial to 8 bit parallel and are transferred by DMA to RAM Error detection is executed in NDC 840 and if the error is les...

Page 7: ...ta write operation the ID read is first executed to search the designated sector On finding the desired ID field the write gate is opened and writing is executed Write data are transferred from the host to RAM then from RAM to NDC 840 where they are transformed to serial data As the ECC is generated by the ECC Generator the data are transformed into the MFM pattern and transferred _ to the disk Af...

Page 8: ... illegal command des ignated unit address etc WR IT E I NDEX AM ENABLEO AM FOUND READ GATE READ DATA WRITE DATA 6 MZ 5600A 0000 I000 2000 rLrJ r I l__ A __j Magnification of the A Part 0 t I 2 3 I 0117 0367 0617 m 7 ...

Page 9: ... GND 11 GND 14 MFM WRITE DATA 13 MFM WRITE DATA 16 GND 15 GND 18 MFM READ DATA 17 MFM READ DATA 20 GND CN2 connector designated pin No t 19 GND 19 17 15 3 ODD o ODD 0 20 1816 4 2 4 2 Drive Interface Driver Receiver 1 Control Signals All the signals of the CN1 connector and drive selected signals of the CN2 connector are like the following I driver NS7438 or compatibles I SV I receiver I t 6m max I...

Page 10: ...ive has reached the normal rotation speed Seek Read Write operations are executed only when this signal is Low This is a pulse signal to seek the head Seeking is made one cylinder per one pulse By selecting the jumper plug on the board the following two ways of seeking are made available 1 Normal mode Seek Seeking is made per every pulse 2 Buffer mode Seek High speed seeking is done by the high sp...

Page 11: ...Write opera tions 2 AMW AM WRITE Active high this should be active when data address mark including the missing clock are to be written For writing the index mark of the floppy AE1 is also necessary 6 Read and Other Systems Input and Output 1 RDM RAW DATA M An active low input signal is necessary to recognize the internal sink field it is a gate signal for the bit counter of the raw data Therefore...

Page 12: ...EARLY DATA NORMAL DATA LATE CLOCK NORMAL CLOCK NORMAL DATA LATE DATA EARLY DATA NORMAL DATA When the precompensation select is internal precompensation is added 5 4 Timing 1 Mode Set Input oil 9 8 no I AI AO I CS JI HOLD 8 Dl oil 6 8 Dl 3 Read Input Output 1 Read Clock and NRZ Output Data b ORCR I v BIT SEL lo b I DO logic 1 0 I ORDT yp lyp 1 8DO 8 101 OAMF 7P lyp no 11 6no 2 Read Clock in Read op...

Page 13: ...ks with the power on A judgement of good or bad is shown with the SELECT LAMP of the drive and the LED of this controller 1 SELECT LAMP The normal action of this lamp after the power is turned on is to light in twenty seconds then immediate ly go off Abnormal cases include the following If the spindle motor of the dirve does not rotate the drive is bad or the power system of the drive is bad llf t...

Page 14: ...em is normal 6 4 5 Impossibility of Command Acceptance 1 Host Interface Circuits RCSET Ill Aa AJ ts 1 I _s lSIU_f 6 110 11 y 8 J1 The NG lamp lights MZ 5600A a Confirm NDC847 8G Pin 2 13 5V TL497 88 is bad Peripheral circuit of TL497 is bad b Confirm NDC847 8G Pin 8t 5V 2 0V NDC847 is bad c Confirm the REad data from the disk NDC842 7G is bad NDC840 4E is bad NDC846 4G is bad 74LS123 8H isbad 26LS...

Page 15: ...a If NDC840 4E Pin 1 stays High NDC840 is bad NDC848 4B is bad The host interface circuitry is bad 6 4 6 Read Mode CD The compelte IRQ does not rise The host interface NDC848 4B is bad 14 129 lllmr lJI lfl1fnt 149 G j 151 141 lsJ 151 rg m Q pV mmrQ NDC840 4E is bad DMA lt started operating but it always gets an Error Reconfirm ltesm a Recoefirm NDC847 8G Pin 2 13 5V TL497 8B is bad The peripheral ...

Page 16: ...T BUF Transfer Rate MZ 5600A When data are transferred between the 5 FXD and host data shall be accomdated temporarily in a buffer register Transfers can be executed at any t ransfer rate 3 BUF area A buffer area can be allocated as one area of Main Memory 2 3 DUAL BU F Transfer 1 RAM P M 6 RAM HOC PROGRAM area BUF 0 BUF 1 area Either BUF is a 1 SECTOR BUF 2KB CHIP RAM maximum SECTOR length 512 By...

Page 17: ...EL 2 82 HEADSEL 2 D3 DRIVESEL I D4 DR I VESEL2 85 DRIVESEL3 D6 DRIVE SEL 4 D7 AM WRITE AM FOUND AM FOUND READ OATE WRIT E OATE SECTOR WRIT E PROTECT TAO I TAO I TAO 2 TAO 2 TAO 3 TAO 3 TAO 4 TAO 4 SERVO VSS Signals in parentheses are used for SMD 1 F 16 4 1 Floppy Interface NDC840 AM ENABLED AM FOUND NRZ R EAD DATA READ GATE READ CLK NRZ WR ITE DATA w g AM WRITE WRITE GATE HOC READY WRITE FAULT S ...

Page 18: ...to an addressed memory in the DMA write cycle When a DMA channel is designated to ttie 1 0 mode this signal is output by handshaking with READ or WRITE 11 ADRE This indicates that HDC is executing DMA and reading commands and that the addresses from HDC are effective 17 MZ 5600A 12 HRO This is an output signal which requests a control over a system bus 13 HLDA This signal answers to HRO and indica...

Page 19: ...1 TAG2 TAG3 BUS CYLINDER HEAD CONTROL SELECT SELECT SELECT BITO 1 1 WRITE GATE 1 2 2 READ GATE 2 4 4 SERVO OFFSET PLUS 3 8 8 SERVO OFFSET MINUS 4 16 8 FAULT CLEAR 5 32 AM ENABLE 6 64 RTZ 7 128 DATA STROBE EARLY 8 256 DATA STROBE LATE 9 512 18 5 2 2 2 Input Signals 1 UNIT READY This indicates that disks reach a rated revolution and heads are on a recording zone When a drive is in fault this signal ...

Page 20: ...dicates that it was not able to detect Track 0 within a specified time after Restore 2 ERROR STATUS MZ 5600A In a Read Write execution any error are shown in Error Status BIT Description NO STATUS 07 LOST DATA Transfer rates of CPU and HOC cannot follow a disk drive and HOC 06 CRC ERROR CRC or ECC Error is found 05 RECORD ID is not found NOT FOUND 04 03 DRIVE CHECK Receives a fault signal from a d...

Page 21: ...on mode in the second Byte Read Write Mode To output Read Write gates in accordance with the Read Write flags of the Command Code Check Mode To not output Read Write gates by ignoring the Read Write flags of the Command Code 1 1 CHO ADR 16 BIT ADR REG of DMA CH 0 in H L 16 bits 12 CHO BYTE 16 BIT H L 16 bit Regster to indicate and select a number of transfer bytes of DMA CH 0 Sets 2 complements 13...

Page 22: ... AND POSITIONS 1 Pin Assignments Pi n th 110 Pi n Pinttl 11 0 Pin PiottL 11 0 P in Pin ltl 110 Pi n NAME NAM E NAME NAM E I 0 i NDEX 1a 0 Jis 2 25 I TNlltx 87 I DS 2 2 0 VCOCLK 1 4 0 iiTRTII 2 6 I cr m 8 8 I D I R 3 NC I 5 0 S T E P 27 N C as I S T EP 4 0 m 16 0 MS I 1 28 I VC I 40 I 1IS I 1 5 0 PI I 7 0 W GT 2 9 I F I I W GT 6 0 RWC 18 0 HS 2 3 ao I RWC 42 I HS 2 8 7 vue 1 9 GND 8 1 vcc 8 GN D 8 ...

Page 23: ... seek completion 10 TRACK 00 CONT When low indicates that a head is positioned at the outermost cylinder 11 WRITE FAULT CONT When low indicates that a drive has an abnormality and Read Write is not executed 12 READY CONT When low indicates that a drive reaches a normal re volution 13 INDEX CONT A pulse per revolution indicates the start of a data track 22 4 COMBINED CIRCUIT OF NDC847 AND NDC842 ND...

Page 24: ... AO A3 Address Input pins to select a transfer register buffer and mode AS A2 A1 AO INPUT INN OUTPUT OUTN 0 0 0 0 0 0 0 0 1 0 0 0 Re Switch 0 0 1 I dA Mode Set 0 1 0 Read Hoat Data Statue 1 Set 0 1 1 Host Data Request Set 1 0 0 HDC Data Request Set 1 0 1 Ho t DMA Eod Reset 1 1 0 HDC Data Set 1 1 1 Status 0 Set 0 0 0 Abort 3 IOGN 10 Enable An input pin to enable INN and OUTN input pins 4 INN Input ...

Page 25: ...MMANDS 4 1 1nputs 1 Read Switch A7 Address X X X AO X 0 0 0 0 L L J D7 DO Data I I l ost Data equest nable HRG s W1N W2N W3N W4N W5N W6N W7N s s s s s When this command is executed data of the Switch SW1 N SW7N and status of HRG are transferred to 8 bit bidirectional data bus DO D7 24 2 Read Host Data A7 AO Address X X X X 0 0 0 L L D7 DO Data When this command is executed data and commands of Inp...

Page 26: ...T1 19 or NDC842 2 has an internal linear circuit and receives a digital signal 3 compact and requires fewer parts in order to build circuit in comparison with a circuit using discrete parts 4 non adjustable and reliable 5 functions as data transfer VCO of ST506 5MBit sec 6 16 pin single line IC and mountable as a regular IC 7 power supply DC 5V 25 1 3 Pin assignment NO SYMBOL 1 I N 3 2 VEE 3 I N 4...

Page 27: ...D OUTPUT WRITE OUTPUT 2 Structure of the Read Block JVCK VGQ CLOCK I CLOC K 2 f CLOCK I KDM JKR I IKR2 IDS I DRIVE SE IDD I Dll2 JRS E IRSN IRSL L I CLOCK SW CL AMP GEN DETECTOR 1 SE L CTOR 1 PHASE COMP 1 DATA SEPARATOR 1 2 2 OCWP CLAMP ORCK REA1l CLOCK ODDO OCGH OCG L ODCH ODCL ORDT READ DATA O u F IAE 0 I A fW MI SS ING DETECTOR AI POUND 3 Structure of the Write Block I FC H C L rG OCK M M FM GE...

Page 28: ...lock 3 3 Clock Output 1 2FC 2F CLOCK This inputs a half circle of the 4F Ciock 2 RCK READ CLOCK In Read operations the clock generated from the VCO clock is output synchronically with Read Data In non reading a negative clock of 2F CLOCK is output This is temporarily set high at the switching point with 2F CLOCK 3 4 Raw Data Input and Drive Select Signals RR1 RR2 DS1 This inputs receiver output of...

Page 29: ...4ne 2 MFM Data OWWD Data Bit Clock Bit Write Precompensation Precompensation Mode INT Data Early Data Nromal Data mi n7 n a xl8oa min 7 ne 81 5no max 18oa Late Data Early normal late Same for Clock Bit DMD Output 2 Precompensation Mode EXT IPED I PN D 1 IPLD ODWD typl 1 2 no __ 28 ...

Page 30: ...1 2 1 D A36 B 35 A 35 B 21 B 12 B Ill B 18 A 15 8 1 7 A 12 6 8 szq A 2q B 2i A 28 B 2 1 2 7 B 26 A 26 B I Ag B 24 A24 B 23 A 23 B 22 A22 r 8_A q I I 1 1 l 14 2 SB I s245 y C4 0 1uF t8 A B 3 t 7 4 r 4 s s 7 4A t3 1fT Jj t T 1 q I IR 6 2 45 S RESET CS HADR1 HADRO DWR DRD DRQ JNT R HD7 H D6 H DS H D4 HD3 HD2 HDI HDO 00 0 D 0 c i c C D 3 ...

Page 31: ...T JRQ i liiQ _ _ _ _ _ _ _ _ _J D l rnl 7_ jl I q i IWilti tii 9Rl I m 0 I 0 I CV S SEl f fll 0 t1R l I soJl u o 2 I _3 _ _ r 6 L i m d tlj L Slll1 I f IAS S r AQT I U3 m IK Rn t lcs le J li ls tl fl thiiD T 0 4 2 2 4B IJC IJC IJC IJC AJC 45 144 4 7 f4B 0 I A r 5 7 Jf U T 31 oo rPuT 1 2 43 53 Si LS J 12 l Set l S 123 1 L1 ll f T AO Ul 3 la Sfl fi 4f ll 2 jj Xj l 3 ff C 0112 G CII OC 21 01 A EOIO M...

Page 32: ...ATf 2 AM FOUND l3 WRITE DATA ll a AM ENABLE 9 AM V RITE 1 3 WRITE GATE 4dWRPT g 6 TAC 2 t 82SET 2 f1 T AC I TAG I tJC g REDUCED WRITE CURRENT 4 HEAD SEL 2 3 HEAD SEL2 I Jt3 HEAD SEL2 2 41 DRIVE SEL ECT I DISK CTRL DATA 4FCLK lllfil PHASE 14 tAITIUUSET OUT IS f HAEAII ME J I G 42 DRIVE SELECT 2 OIR IN J H SFl 2 5 STEP 04QEXC 17 G 1 f Q I IM51FP NC J NC 29_ 8_ RESET 74 DRIVE SELECTED TRACK _ SEEK C0...

Page 33: ...Y 48 I NnFX I D SEL I u s 2 in lV 2 N 2 1 4G 2 2 ll IN s p H Cl V 7 31 il lu F ell m 19 43 I uF t l2 filu 9 13 8 A 7 El E o DSI I 16 4 D SFL 2 17 A c 3 _q G DR m L5542 l 7 RM4 2l il r f W 1 21 si I Lvv IS 22 _ 1 1 1 Gvvv l 12_3 l f wv 11 1Lv l y 3 1 24 81 I V 125 kfvl I L v 1 1 2 L i_Lvv IJ RMJ bi 22 n 1n 1 l 117 I CN I I 1 f R iT 1 2 1 3 5 7 9 f 11 13 15 1 7 1 9 21 23 25 n 29 31 33 7 7 I I RED CE...

Page 34: ...d 2C __6_ 2 T o RE 1 511 I f L i I 11 a 1 1 38 _ 3 1 2 C y u I 2 I 8WF 1 21 INTR G HR LS 2 L__j 10 MFM G 3 4 43 BUSR EO LSI25x4 RAM V L 4 2E 4 1 L x3 2 a I 41 BLJSACK 11 A_ K f t3j 1C p_ _ _ _ _ CS2 LS 4 1 A IRF LC 3 _C_S_I RS f 1 K n 42 1 lhJAQ __ PU I WAIT A 1 Af H 5llC r b CSO 3 5 l i JMI lA Q HL IAA RESET 2 RE T b J rA 7 DATM E Ar 0 OR A H I A Af P 2 TL r c Af P 3 1 VC I A R4 1 u F c 13 H 1 t ...

Page 35: ...A 7 __ J RAM WE MEM QE f r 1r r26 26 4i I t Ifi t t E A J I I L 1 A I 14 l i i l A 2 1 l UL AJP l f A 4 4o A 5 14 I A 6 l I A7 As e312C I A gl22l g I L I 2j i PI I I J P4 r wt_ lr LEOSET J 7 l NG LID2 6 2 KJJ a E fl PU2 ...

Page 36: ...OC 847 8 CI CI 1 hfMpt l m A R 1 1b AE RS i _ _ t IUA2 lE IIAtl TE l o 1 A IIIRITE 3 ltUO 6 11 1 AN 8 tA 11 2S lSC4 NOC 842 11 r AI l q 4 12 7 1 0 w r H 0 2 i1C 2 1 CJ l G X1 33 OAMJ AI J Oi Wf 0 Oll i T REA T Sf 13 5 OR Clf 7 Cl 2HS3i ...

Page 37: ...I 35 7 2 3 II 4 R_ Vc t 4 ll illc 3 ea c2 1 In LJ 17 1921 I c 13 AI 2125 27 5V 47yl 33 v BB 1 2Ka l1 l 23 3l n uv n n a_G L2 c C o Cl o n 36 dB q3 9 Rib 150 t 4 z I Z 2 44A7 48 5 22fJpF T GN9 Ull 1 3 II V L__ _ _j t IOO uH l L 4 V _ ______ _ _ ___ 7h V GND MFM W DATA MFM WDATf MFM R DATA MFM R DATA DRIVE SELECTD GND IGND MF W DATA MFM W D TA MFM R D ITA MFM R D ITA WRITE GATE RE SET SEEK COMPLETE ...

Page 38: ... 37 MZ 5600A ...

Page 39: ...Z25 43 OCT0000511015 AE N c Capacitor GR40F104Z25 44 0 C T 0 0 0 0 5 1 1 0 1 5 AE N c Capacitor GR40F104Z25 45 0 C T 0 0 0 0 5 1 1 0 1 5 AE N c Capacitor GR40F104Z25 46 0 C T 0 0 0 0 5 1 1 0 1 5 AE N c Capacitor GR40F104Z25 47 OCT0000511015 AE N c Capacitor GR40F104Z25 48 OCT0000511015 AE N c Capacitor GR40F104Z25 49 OCT0000511015 AE N c Capacitor GR40F104Z25 50 0 C T 0 0 0 0 5 1 1 0 1 5 AE N c Ca...

Page 40: ... 622J R8 96 OCT0000411015 AC N c Resistor CRG 1 8 361J LR9 97 0 C T 0 0 0 0 4 1 1 0 1 7 AC N c Resistor CRG 1 8 431J R10 98 OCT0000411028 AC N c Resistor CRG 1 8 562J Rll 99 OCT0000411010 AC N c Resistor CRG 1 8 101J R12 100 OCT0000411010 AC N c Resistor CRG 1 8 101J R13 101 OCT0000411003 AP N c Resistor SN14 L3A 10 J l R14 102 0 C T 0 0 0 0 4 1 1 0 2 2 AC N c Resistor CRG 1 8 122J LR15 103 0 C T ...

Page 41: ... MZ 5600A SHARP SHARP CORPORATION Information Systems Group Quality Reliability Control Center Yamatokoriyama Nara 639 11 Japan 1986 June Printed in Japan ...

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