Sharp MZ-5600 Service Manual Download

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Summary of Contents for MZ-5600

Page 1: ...4 5 Memory Control Logic 24 6 I O Decoder Logi 28 7 DMA Interface Log 31 8 MDF Interface circuit 35 9 Printer Interface 44 10 ATC Real Time Clock 46 11 Programmable Sound Generator Interface 47 12 AS 232C Interface 48 13 Software Timer 51 14 Displav Interface 54 15 KeVboard and KeVboard Interface 76 16 Power Circuit 80 17 Self Cheek 84 18 Terminal View of Cable 86 19 Circuit Diagram Parts Position...

Page 2: ...acity video screen memory and bit map display 4 One or two mini floppy disk drives each of 640KB are provided as a standard feature And the MZ5645 is 10 MB Hard disk is standard 5 Powerful standard I O system interface 6 Integrated sound generator 7 CP M86 as the standard operating system MZ1P02 Hard Disk I F Z5645 Expansion RAM PWB 256KB MZ1R11 MZ1R22 G 7 r Expansion Unit Cable MZ1C33 Numeric Dat...

Page 3: ... 6 320 x 200 12 C 640 x 400 1 640 x 200 2 320 x 200 4 8 colors can be specified for each dot 8 gradations available with the Available on a monochrome t dedicated monitor monitor 1 D13 with a 640 x 400 matrix Display capacity 40 or 80 characters on each row Controlled by software The number of rows per screen is programmable Character cell 8x8 8x16 Superimposed 3 pages Multi window 4 windows Scrol...

Page 4: ...isk drive I F PWB Attached to keyboard Additional drive to be installed in the System Unit External drives 10M Bytes 640 x 400 dot matrix 640 x 400 dot matrix 640 x 400 dot matrix it Color monitor MZ 1 014 Table 4 MZ 5600 Description For printer attachment Built in 13 byte RAM Two built in drives plus two external drives Programmable between 110 and 9600 bauds For MZ5631 MZ5645 is standard For MZ5...

Page 5: ...splay MZ1D18 Table 11 Product 640 x 400 dots 15 inch flat square non glare outline semi black type color display for use with the MZ 5600 Specification Tube used 15 inch 90 deflection flat square type non glare treated Input signal R G B three independent TTL polarity Horizontal TTL positive polarity synchro nization TIL 9 W pol d signal Vertical synchronization signal Deflection 24 86KHz horizont...

Page 6: ... 80A _ I 510 CPU SOS6 2 SMHz IPL ROM 16KB Timer Z SOA CTC GDC 07220 DMAC 8237 FD55F o o Driverl receiver Real time clock RP 5C01 Semi custom LSI M mapper WDC Audio output D r Back up RAM Sound IC AY 3 9812 Bus multiplexer VRAM 96KB I IExpansion VRAM I I 96KB I L ____ i a o lots r 1 1 1 2L3 14 5 L __ __ __ L__ __ J 5 Semi custom LSIt O T f video controller VDCl VDC2 Expansion RAM 1 MZ1R22 1R11 HO I...

Page 7: ... hard disk SYSTEM DISK DEVICE SYSTEM DISK 640KB MFD 0 HD 0 320KB MFD X SFD X 640KB MFO format 256 bytes sector 16 sectors track 80 tracks side Must be created by DSKMAINT Must be created by DSKMAINT Creation and bootstrap are not possible Creation and bootstrap are not possible 2K bytes block 128 directory entries Prior to the use of a fresh disk it becomes necessary to format the disk using OSKMA...

Page 8: ...blocks i Interface block Interfaces the BOOS with loes ii loes code block Control program for the input output device handler called the Input Output Control System lOeS iii loes data block Parameter and work area used for the loes The MZ 5600 system can be upgraded by using an IN STALL command which integrates the optional loes module into the BIOS The above figure on the right provides the memor...

Page 9: ...rrupt vectors reserved for the 8086 System reserved interrupt vectors Interrupt vectors used by the IDeS Interrupt vectors availeble to the user Interrupt vectors used by the BOOS Interrupt vectors available to the user Interrupt vectors used by the IDeS TOD KEY RSPARM Time and date set up and display utility Definable key set up utility RS 232C parameter set up utility ASSIGN Logical physical dev...

Page 10: ...een one at a time PRINT Out Printer output from the background PROMPT In Setting command prompt SET In Changing the value of the character string SORT Out Rearranging the data in the alphabetical order or reverse alphabetical order TIME In Display or setup of the time VER In Displaying of the MS DOS version number VERIFY In Verifying the disk contents d Program developing commands Command In Out F...

Page 11: ...e 0 32KB RESERVED 128KB Auxiliary area for options Expansion RAM area 266KB XACK 1 1 o 64KB 192KB 1 o 1 1 o o Divided into the 8086 display cycle o 0 0 0 1 100 1 010 Read and write attempt from 8086 Includes 1 to 7 Mits 1 r 1 128KB I I Expansion I I By Bank I I I Select 128KB 128KB 128KB I 612KB I i _______ L ____ _____ 1 _ ____ 1 __ I XACK XAcK External Raady signal 1 XACK 128KB 1 r o 16bit BUS 2...

Page 12: ...NG appears on the video monitor and the loader is loaded from Drive zero into the system according to the information contained on sector 1 of track O When loading is completed control skips to the first address at the loader If an error occurred during loading the system provides the following message display and waits until a new diskette is placed in the drive When the new diskette is inserted ...

Page 13: ...DING display I System disk I Internal MFDO I Not ready or No system disk NO I Is there HD I F I r I yes NO SYSTEM DISK I J NO I I f I HDO ready yes NO SYSTEM DISK WAITING FOR HARD DISK J NO I System on HD I r I yes NO SYSTEM on MFD HD I J I SYSTEM LOADING I Ir Loading from certain drive 12 ...

Page 14: ...J I 1Z 1 R09 CAD PO 101 A I LS I LZ90E07 L J inllll l 1 KX4 MP ________________ Ir IU B I C I r I I O RAM I 256MB OPTION 111 1ltl1 Z 1 RZZ Q RAM w256MB IPL ROI I 16MB onCTION I x BIT r l I I r l SLDT I i I I SlOT 2 i I I 1 11 1 uos I I I SLOT 3 I I I I SLOT I I 16BIT I l I I SYSTEM I I SLOT 5 I MZ 1U07 L l j BUS I ADSTB H L J SYSTEM DATA BUS 16 SYSTEM COMAND BUS OMAC 8237A VFO HA 16632A CTC l LH 0...

Page 15: ... pins DIP package 14 Pin configuration top view GND Vcc 5V ADl ADl5 AD18 A16 S8 ADl2 AI7 S AD11 A18 S5 AD10 A19 S6 AD9 BiIE S7 AD8 IINIJiX AD7 m AD6 8086 2 HOLD RQ GR AD5 HLDA RQ GTI AD lrIf IOO AD8 1I iO Sf AD2 DT 1f ST ADI IiEN Sli ADO ALE QSO NIl I INTA QSl INTR TEST eLK READY GND RESET Fig 11 Terminal names given in parentheses are used for the maximum mode The MZ 5600 uses the 8086 in the max...

Page 16: ...t I Timing status I r J f r r j and control f logic 16 16 16 1 16 _L J_ AH 8 AL 8 BH 8 BL 8 CH 8 CL 8 DH 8 DL 8 SP I6 BP I6 SI I6 DI I6 General purpose register file Parallel 16 bit I logical unit Execution unit EUI Fig 12 INTR Maskable interrupt request input Non masklble interrupt Reset input request input READY Ready input 1 23 TEST Test input RQ IGTO Request grant 3Q RQ IGTI output MaxI 1 HOLD...

Page 17: ...d by word 16 bits 0 1 High order byte 1 0 Low order byte 1 1 Not used 32 RD Read control OUT Active low output to indicate the timing of read operation from memory or output I O ports 22 READY Ready input IN Indicates that the memory or peripheral device is ready for data communica tion If this is low the CPU completes the current read or write cycle after it is set high 18 INTR Maskable inter IN ...

Page 18: ...trobe used to load address information which is output from the CPU on time division scheme into external latches Indicates the direction of data transfer to an external data bus buffer Enables the external data bus buffer When receiving a Hold request the CPU relinquishes bus access authority and enters the Hold state immediately after completing the current machine cycle Indicates that the CPU a...

Page 19: ...wer on reset signal can be procIaad by connecting a resistor and capacitor to this mterml q D F e EFl Quartz controlled OSC 4 4 8288 bus controller Highlights 1 Outputs with a large number of fan outs CKO D FFl 2 Advanced write control outputs AIOWC and AMWC Pin configuration 1 0 bus mode t ontrol input lOB C6V Ctock input eLK Stlllu input ST I StICu input Frequency divider 11 3 SYNC Fig 14 Functi...

Page 20: ...ess information from the CPU OUT Provides a data enable signal to the data bus transceivers on the local or system bus active high OUT Controls data flow between the CPU and memory or I O devices When this pin i high the CPU is enabled to write data into a peripheral device when it is low the CPU is enabled to read data from the device IN If this pin is set high with tha lOB input held at low all ...

Page 21: ...5V power supply 2 Automatically produces a Interrupt vector to the CPU 3 Priority interrupt masks at each interrupt request terminal and vector address specification are all pro grammable 4 Controls up to 64 levels of interrupt requests by cascading the 8259 5 TTL compatible Pin configuration top view Chip select input CS_ Vcc Write control input WR Read control input Ri5 07_ 06_ 05_ Bidirectional...

Page 22: ...ce Controls command write from the data bus Controls data read onto the data bus All data and command transfers to or from the CPU is performed through this bidirectional bus These lines are output when addressed as a master and are input when addressed as a slave The master uses three bit code to specify a slave via these cascade lines The slave compares the code on the cascade lines with its own...

Page 23: ...he CPU With this model the program is reset by the soft ware using NMI in order to retain the AAM except for such a wild program run that may destroy the NMI vector or NMI routine 2 Since this unit is the system of nonnally non ready the ready signal is issued to the CPU or DMAC only when a valid memory or I O is accessed When an invalid memory or I O is accessed it makes the system as if halted T...

Page 24: ...Y READY RDY CLK CLK 2 Operational description Yoeset For reset of the 8086 CPU the alarm Signal from the power supply and the rising edge of 5V atthe time of power on are detectad by the CR time constant The reset signal to the CPU is Internally synchronized with the clock by the 8284A Refer to the section dlscuulng the power supply unit for alarm timing 2 Ready Because the MZ 5600 employs the non...

Page 25: ... CPU in the not ready condition If the CPU should go into the next bus cycle it awaits for return ing of bus control while executing the wait cycle 4 DMA transfer is dona under the control of the 8237A 6 As the DMAC releases HRQ upon completion of DMA transfer the system bus is changed from the DMA bus to the CPU bus and the wait circuit is reset after enabling the 8284A again 6 The CPU executes t...

Page 26: ...signal is output when the BR Ai 1 MRDC and AMWC signals are all active The DACK2 is used to output the RAS signal during refresh regardless of the chip select signals DRAM 25 MZ 5600 3 Dynamic RAM read write timing o SMHz Read cycle T2 TB TW CLK86 ADR __ ______________ L ____ RA CA 11 DRAM ADR DRAM DATA OUT o 8MHz Write cycle CLKIIII R A __________________ ______ __ 86DATA OUT 1 A CA _ _ _ _ I DRA...

Page 27: ...otection by itself the protect function does not cover this area 2 Task register Since MPL is capable of managing four tasks choice of task must be done in the following manner I O address 60H Write only 03 02 01 DO I I I I I I IL Task 0 Task 1 L Task 2 Task 3 EX 0001 Task 0 in execution 01 00 Task 1 in execution 3 Protection memory Depending on the nature of the task read and write to the task is...

Page 28: ...he protection memory area Theory of memory protection For instance the protection RAM area 10000H of the bank 1 contains 1010 to enable the 1 KB area of the system RAM 1000H 103FFH for access by tasks 0 and 2 If the system RAM area of 1000H 103FFH is tried to RAM C1K x4 I O Task 3 ection Logic read or write during the execution of the task 1 with 0010 in the task register the data 1010 is sent fro...

Page 29: ...I I B A 6 I O DeCODER LOGIC 6 1 Block diagram LSI88 5Vo G YO IOACC J G YI A G A7 Y2 A8 7E YS A Y4 B Y5 I AS C YS Y7 A4 S A9 LSI38 A9 G YO ALE l G YI l G Y2 SE YS A4 A Y4 A5 B Y5 AS C YSlo Y7 Fig 33 As shown in the above figure two integral decoders LS138 s are used to provide chip selection for each I O device on the CPU board 28 B I RESTORE SS SP 1 END CSDMA c CSPIO CSFOC CSPIC 1 OWait CSPIC2 CSU...

Page 30: ...0 PIC2 S259A SLAVE AOO 7 0 1 0 1 X X X X OMAC high order address latch 104 7 0 1 1 0 X X X X PORT A 100 7 0 1 1 1 X X X X PORT C 100 3 1 0 0 0 X X A1 AO Reserved 100 3 1 1 1 1 1 A2 A1 AO Reserved 0 0 0 0 X X A1 0 GOC j lP07220 00 7 0 0 0 1 X X A1 0 WOC T 00 7 0 0 1 0 A3 A2 A1 0 VOC2 H2 00 2 0 0 1 1 X X X 0 VOC1 H1 00 2 0 1 0 0 X A2 A1 1 RFLI OS 10 0 1 0 1 X A2 A1 1 RFL 11 OS 10 0 1 1 0 X X X 0 1 1...

Page 31: ...nterrupt by ACK input to Centronics I F OUT Cantronics I F STROBE output U IN Centronics IIF ACK input OUT Not used 3 The desired bit of the output to Group C may be set or reset USing the control register 013H 4 The bit PC6 is an interrupt enable flag IINTE and is set or reset by the CPU AFTER PlO Input mode FFH Mode input Input mode FFH 5 While the ACK may be read by PC3 is needs not be reed as ...

Page 32: ...W ON CPU Input mode L8387 ID2 DIPSW7 SW1 Svstem D SW See separate page 103 DIPSwa SWS ay dip Itichfunction Function Factory setup OFF For u of the hiQh resolution dilPlay 400 reuters SW1 ON For u of the mlddl resolution dilPlay 200 restel1 SW2 OFF Normally OFF ON Self check mode SW3 R rved SW4 SW5 OFF 8MHz CPU clock ON 5MHz CPU clock SW6 OFF 8087 arithmetic processor not in use ON 8087 arithmetic ...

Page 33: ...old conver sion circuit receives this signal it puts the CPU into the non ready state to open the system bus At the same time the hold acknowledge signal HLOA and DMA enable signal cB DMAE are returned to the DMAC to start DMA transfer With the 8237 DMAC it is possible to control DMA transfer of 16 bits in total 64 KB Aa A7 issued by the DMAC itself and A8 A15 which DBO 7 are latched by ADSTB at t...

Page 34: ...mination of transfer 10 Software DMA request 11 Variable active levels on DREQ and DACK signal lines 3 Block diagram DEC INC DEC ToP TEMP WORD TEMP ADDRESS COUNT RE 06 REQ I6 RESET CS READY CLOCK IOR IOW lmIm MEiiW 0 READY HLDA ADSTB AEN HRQ CLK RESEr I Wl 2 Dl CK8 I RFX 8 2 mEQl mEQO GND AO A7 AEN READ BUFFER READ WRITE BUFFER ADSTB BASE I BASE CURRENT I CURRENT CONTROL ADDRESS I WORD ADDRESS I W...

Page 35: ... CPU has relinquished system bus access authority OUT Active high address strobe used to strobe the high order address byte OUT Used to enable the output of the latch holding the high order 8 address bits to output them onto the system address bus The AEN is also used to disable other system bus drivers during DMA transfer OUT The 8237A uses this hold request Signal to request the CPU for the syst...

Page 36: ...channel 1 is opened 2 When the FDC finds the corresponding sector on the FDD a DMA request DRa is issued to the DMAC 3 When the DMAC receives DRa the DMAC issues a HRa to the CPU 4 As the bus line is opened and HLDA signal is returned when the CPU receives HRa the DMAC sends back OACK signal to the FOC 5 Data transfer takes place between the FOC and the FOO under the bus control by the OMAC a8 3 T...

Page 37: ...manner 36 RIGH DEN When High Den 0 the time constant must be CR1 When High Den 1 the time constant must be C Rl R2 Also Ml and M2 need to adjust as their pulse widths affect the reading margin When a SYNC byte is detected or when the ID field is recognized the data are read exactly with an increased gain and the gain is decreased in read n9 the actual data in order to achieve positive reading Forf...

Page 38: ...e the VR2 to set the 2 V waveform to 2 V waveform distance to 990 1010 nanosecond 6 Set the switch to 3 and the frequency rance to 0 5 microsecond and manipulate the VR3 to set the 2 V waveform to 2 V waveform distance to 2 48 2 52 microseconds 7 Set the switch to 4 and the frequency range to 1 microsecond and manipulate the VR6 to set the 2 V waveform to 2 V waveform distance to 4 95 5 05 microse...

Page 39: ... to high width 495 505ns 5 C 5W2 0N VR2 PWB 0 2 1000ns High to high width 990 1010nl 6 C SW3 ON VR3 PWB 0 51 5 2 51 5 High to high width 2 48 2 52 7 C SW4 0N VR4 PWB 11 5 5 01 5 High to high width 4 95 5 051 5 NOTE As the figures in the bottom are the range of values for adjustment it is preferable to use the mean value 38 Waveform r I 25Ons 0 5 scale hotches 1 2V I_ 6OOn 1 5 scale notches 2V 1 1O...

Page 40: ...al description The FDC searches each drive at 1 millisecond to check the ready state when not busy that it when waiting for a com mand If the ready state searched before does not coincide with the ready state searched this time it applied a state transition interrupt to the CPU to inform removal of the disk from the FDD The reason why the one shot multivibrator circuit is seen in the select of the...

Page 41: ...te Clock WINDOW Data Wirrlow RDATA Read Data SYNC VFO Synchronize WE Wri te Enable 40 LPD765 Block diagram DBO 7 DRQ DACK INT RD WR AO TC RESET CS MFM SIDE USO l WDATA PSO l FLT TRKO WPRT 2S I DE READY HDLD FLTR STEP LCT DIR RW SEEK MFM Mode Side Select Uni t Select Wri te Data Pre Shift Fault Track 0 REGISTERS SERIAL INTERFACE CONTROLLER DRIVE INTSRFAC CONTROL LE Fig 46 Wri te Protected Two Side ...

Page 42: ...d write and seek signals from the drive interface signals If RW SEEK is zero indicates RIW if it is one indicates SEEK 36 HOLD 0 Loads the read write head in the drive 27 SIDE 0 Selects head 0 or 1 of a double sided drive If SIDE is zero head 0 is selected if it is one head 1 is selected 38 LCT DIR 0 If the R W SEEK signal specifies RIW this signal functions as the LCT to indicate the drive s read...

Page 43: ... is done within the FDC 1 Medium sensor The host system identifies whether or not a diskette is placed in the drive by first sending a SENSE DEVICE STATUS command to the FDC then reading the result status ST3 from the FDC and identifying whether the MFD is in the READY state or not If the MFD remains NOT READY 800ms after its motor is turned on the host identifies that no disk is in that MFD 8 9 V...

Page 44: ...k 10 M2R In One shot multivibrator M2 resistor and capacitor connection pin 11 M2C In One shot multivibrator M2 capacitor connection pin 12 MFM In Input line to aDign two choices of the FM and MFM modes high for the FM mode and low for the MFM mode 13 RD DATA In Raw data from the floppy disk C Includes two signal components of 1 clock signal and 2 data signal 14 TP1 In IC test pin When IRS is high...

Page 45: ...er RD DATA I I L _ _ _ _ _ _ _ _ _ _ _ _ _ 0 il I GND M5C M5R 9 PRINTER INTERFACE 825PA cs pe5 0 0 S1IDBE Rii WR PAD DATAl fi TA8 RESET PA7 AO AI PCS PHD 1 0 1 Nl oBUSY PHI 1 oc uf Nl oPE PCS PH2 1 oc f Nl OSELEcr L _ _ _ _ _ _ _ _ Do oSRES Fig 48 44 9 Logic description The printer interface uses an integral parallel interface controller 8255 The 8255 has the modes shown in the table at the right ...

Page 46: ...errupt 12 If it is not the last piece of data wait for an interrupt i 9 3 Parallel interface signals Pin No Signal name Direction Table 25 Description 1 STROBE PRINTER Printer samples print data at the leading edge of this signal 2 DATAl 3 DATA2 4 DATA3 5 DATA4 PRINTER 6 DATA5 7 DATA6 8 DATA7 9 DATA8 10 ACK PRINTER 11 BUSY PRINTER 12 PE PRINTER 24 SRES PRINTER 25 SELECT PRINTER 14 23 GND 13 t 9 4 ...

Page 47: ... 13 x 4 battery backed up RAMs 2 8 A timing pulse of 1Hz or 16Hz available as an alarm Pin configuration In order to set voltage stable for input and output pins during power off the real time clock is resistor pulled down except for WR signal which is pulled up to prevent error writing of data at the time of power on and off RD and WR are delayed by the flipflop in order to main tain the address ...

Page 48: ...generator AY 3 8912 has three independent sound outputs to produce chords It contains a general purpose 8 bit I O port and uses the IOAO IOA4 as the FDD drive selector and motor on signals and the IOA5 IOA7 as a bank selector for the memory area AOOOOH through BFFFFH 11 3 Programmable sound generator PSG AY 3 8912 1 Highlights 1 Completely software s ontrolled sound generation 2 Interfaces with al...

Page 49: ...EAD F OM PSG Transfers the contents of the currently addressed register to the PSG CPU bus 1 0 0 ADDRESS LATCH 1 0 1 INACTIVE 1 1 0 WRITE TO PSG Indicates the register data to be latched into the currently addressed register is on the bus 1 1 1 ADDRESS LATCH When in Data mode Corresponds to the register array bits BO B7 When in Address mode DAC DA3 selects a register number and DA4 DA7 is used for...

Page 50: ...n the system sends data If it is off the system stops data send Note Up to two bytes of data may be sent after the CS is turned off Indicates whether or not the system is ready for data reception READY is on if the system is ready READY is off if the system is not ready 1 Indicates whether or not the remote device is ready for operation On if the remote device is ready for data send receive Off if...

Page 51: ...tion SV GND J6 INTERRUPT IEI CONTROL IEO RXDA RiCA TXDA I XCA n Rn WIROYA CH A IIODEII 1i RA CONTROL RXDB TXDB W7iiiVIi 1I0DEII DTRB CONTROL DCDB CH B g TIlT 5 L __ J i mi DO D7 B A CID CE M1 10Ra RD RESET IEI IEO M W RDYA W RDYB CTSA CTSB DCDA DCDB RXDA RXDB TXDA TXDB RXCA RXCB SYNCA SYNCB C O B A Fig 59 System data bus used for data or command transfer between the CPU and ZBO SIO Channel A or B ...

Page 52: ...ollowing procedure is given using the I O port CSAKC CSRET For the interrupt acknowledge cycle the interrupt vector outputted from the CTC is sent to the AL register when read through the I O port 240H For the interrupt restore cycle the data equals to RET1 of the 280 CPU when writing O or 04DH to the I O port 260H 13 3 Channel description CH No I OADR MODE PRESCALE INT 0 210H Timer 1 16 X 1 211H ...

Page 53: ...B TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW T4 CLK8B Rnd CTe DATA OUT jc I l r H 13 6 2 Timing chart Tt T2 T8 TT TW TW TW TW TW TW TW TW TW TW TW TW TW TW T4 eLK I interrupt ecknowtodge cycle Execution of interrupt I MOV AL 20H 1 01 command OUT 30H AL STI I C IRET 13 5 Distinction of interrupt channel The Z80A CTC issues the interrupt vector in the interrupt acknowledge cycle As the vector cont...

Page 54: ...CE when data or channel control words are to be transferred between the CPU and CTC 53 IEI IEO INT MZ 5600 Active high interrupt enable input This signal is used to create an interrupt control daisy chain within the system If there is more than one peripheral device which can be a source of an interrupt within the system their order of priority is determined by using the IEI and IEO Active high in...

Page 55: ...400 COlOR MONO COlOR MONO CHRO CHRO Frames vs IStandard 1 3 2 6 memory size expansion 2 6 4 12 Table 32 640x200 640x200 320x200 320x w6 COlOR MONO COlOR MONO CHRO CHRO Frames vs IStandard 2 6 4 12 memory size expansion 4 12 8 24 3 Usable display type Table 33 COlOR B W 640 x 400 MZ1D14 1018 MZ1013 320 x 400 MZ1D14 1D18 MZ1013 Note MZ1D13 400 raster 12 green display for the MZ 5600 MZ1D14 400 raste...

Page 56: ...TL gates The display control logic block diagram is shown in Fig 66 The display control logic consists of a GDC WDC timing 55 MZ 5600 generators VDC1 video signal controller VDC2 and VRAM Each block can be accessed from both the CPU and GDC since the display cycle is divided into a CPU cycle and a GDCcycle While the CPU treats the GDC as one of the I O devices the GDC functions as a sub processor ...

Page 57: ...CO ADl2 AD 11 AD 10 AD9 AD8 AD6 AD5 AD2 ADI ADO LPEN 1 For text mode only For text and text graphic integral mode Fig 67 AI7 CSR LC4 AI6 LC3 ADIS ADI4 ADIS ADO BLANK VSYNC EX SYNC HSYNC REF LPEN CSR UWiE CAT BLINK LC2 LCI LCO ADI2 RAS OOIN CLC Sync sig nal generator 2xCCLK AO RD CPU interface I O Command Data WR DMA controller interface control I RAM FIFO ROM 16 x 8 DRQ 16 x 9 128x14 DACK 0 0 DBO ...

Page 58: ...and vertical flyback periods 2 Between the execution of a display stop command e g RESET or STOP and that of a START command 3 During video memory access for read write Control signal furnished from the GDC to video memory In dynamic RAM mode this is a basic timing for the RAM When high functions as an address latch timing signal DMA request output not used Indicates DMA transfer busy Not used Acc...

Page 59: ... may be over lapped on each other 4 Input address may be directly output without using the window feature woe block diagram lA0 IA16 0 OT7 la DTO f REGISTER I j DTat rl ADDRESS LATCH J I AR SELECT I CS I 16 W f t Il ALEN PR ROW COLUMN CL r rr 2xCCLK K COUNTER COUNTER K 7 10 BLANK VS Displ in s z1z _w_u_ MRS J L J MAPPING RAIl CONTROL 7 10 DiiiiI _________ J_ Mcr iiifE MRAO MRA6 Ex rnlll IOllic WE ...

Page 60: ...s mapping RAM mapping RAM row addresses 0 6 Address bus output for column address mapping RAM mapping RAM column addresses 0 9 Internal regi ter chip selector input Internal regi ter write input Mapping RAM control logic elector mapping RAM control circuit select Address bus input input address 0 15 Trigger input display clock Used Increment to ROW address counter Blank signal input from PD7220 us...

Page 61: ...er set at anyone time Configuration of WOC and mapping RAM I o r I ADO Al AD 15 Data Mappirg WDC Address RAM 2XCCLK GOC BLANK RAS Mapping Data RAM Address Write Fig 73 60 127 0 0 Row Map RAM 0 0 Initial information is written into the mapping RAM by using the GDC s drawing feature The Fig 73 provides the WDC mapping RAM and GDC configuration The CS of the mapping RAM is always low and is read when...

Page 62: ...I buffer gate signals VDEO VDE2 which are used by the CPU or GDC to access the VRAM Produces display timing control signals LVD 1 timing control block diagram RESET Vcc GNO 00 01 02 CS r p rrrr latm r f 0 0 0 0 r CKO CKl CK2 42 95MHz 28 64 H CLOCK rCLOCK I SELECT DIVIDE r I latch l DCK 2xCCLK CPUA r v t t WE DBD L DECODE MPXER DECOffi f i TIMING GENERATION LOAD OE RCS CRL S L READY RAS GDE Fig 74 ...

Page 63: ...and CASL signals are created from this CAS signal OV input Switches the CASH and CASL signals for CPU eccess and GDC access Also used as a latch timing signal CCAS for the 8HE and AO V RAM data bus buffer enable I 1 GDC data enable CPU data enabla I i XACK output to the CPU 1 VRAM row and column address selact signal input to the S pin of MPX Reset input VRAM address input from the WDC or the GDC ...

Page 64: ...K Prevents RAS and CAS from being set high while the GDC is REF drawing Prevents CAS from becoming active during VRAM refresh AI7 AI6 MZ 5600 CPUT2D CD CPU timing delayed by 2X dot clocks CDE is created from CD OE P t TIE DR DW Fig 78 The OE is created from the latched DBIN so it may be set high only while the GDC is drawing DR Data read by the GDC from VRAM DW Data written by the GDC into VRAM CP...

Page 65: ...onochrome mode e Normal reverse video display for each window in monochrome mode READY CR ID VDC2 video composition block diagram IIRDC IT AB A2 Al 02 01 DO V c c _ j J J J III GND_ lJ J LOAD JJ 110 PORT MW i C r l CR I 1 CLR VRAII wso I RCS WSl r BL i I Fig 81 VSLO l r 1 0 VSL 1 I I r t Q NORMAL 1 01 VSL2_ I REVERCE NPXER r 1 0 5L DCK L r L 510 BACK 511 t OR t PRIORITI GROUND r BORDER COLOR COLOR...

Page 66: ...e I O port is switched for each window using WSO 2 Monochrome mode reverse video logic I O 1 4 to 1 port selector so ifS OD WSID BLD 510 511 512 Fig 86 MZ 5600 C In the monochrome mode three pieces of display data are combined OR Reyerse video is accomplished on the data on the I O port selected by WSO and 1 To prevent the border area from being reversed the display data is combined AND with the B...

Page 67: ...te number depends on the following color numbers set in palette registers 141 H 010 09 08 Color number for register No O 143H 010 09 08 Color number for register No l 145H 010 09 08 Color number for register No 2 147H 010 09 08 Color number for register No 3 151 H 010 09 08 Color number for register No 4 153H 010 09 08 Color numberfor register No 5 155H 010 09 08 Color number for register No 6 157...

Page 68: ... 1 During display or RAM refresh cycle the VDEO 2 GDE and CDE are all high leaving the bus buffer outputs off 2 For reading aecess from the CPU the pertinent VDE is set low and the CR L of the LS374 is set high to latch read data 3 For writing access from the CPU the CDE and the corresponding VDE are set low 4 For drawing access from the GDC the GDE and corresponding VDE lire set low However if A1...

Page 69: ...AI A y VAS A7 B CPU address bus AS y VA7 LS251 X2 Fig 96 68 v Shift register clock In the 320 dot mode the internal VDC1 clock is obtained by halving the Dot CK S L for the 640 dot mode as shown below 640 dot mode dot Ck S L r r 320 dot mode dot Cl S L Fig 97 vi CPU ICC8II to VRAM Al AlS Al7 Al The CPU is clocked asynchronously with the GDC The VDC1 latches the and from the CPU and VRAM chip selec...

Page 70: ...R G B with the sync signals HSYNC VSYNC providing OfA conversion on the resulting signal and outputs it as a monochrome video signal via an emitter follower 1 2V_ _ Display section D 4V DV f 400 200 cycles Level after the display is attached White level Single cycle display Black level Border color sec on in the bottom area of display 6 21 cycles During VSYNC period 8 3 cycles Border color section...

Page 71: ...g S L 1 I ________ __________ r l ______ __ LOAD 14 190ns max 120n8 max WDO l BS invalid X valid X invalid VSLO 2 R G B Fig 102 VDC1 VDC2 internal register write timing cs 21 4mi DO 2 X valid t 0 min Fig 103 1 HI LS04 H2 HI LS04 H2 HI H2 ...

Page 72: ... I aa J 0 I I I 11 6 1 I ___ J I I I I L 8 5 46 6 ____ I il 20n ma ___________ r L I I I ______ j I 15 9 792 CPUA ____ JI L rc _______ __ _____ _ l 9 2 88 1 LOADl 1 L ___________________ SlL___ r J CRL 1 jo 9 4 86 7 I OofHOO4 CI U Timin Oof HOO8 a of H301 Qo _ _of 1103 _ 11111 _ Output of G213 CPU command latch VDE I J lC 11 2 1 2 accessed 0 2 1 t 11 2 682 I if accessed J J Ir 9 4 52 7 CDE _ _ _ 1...

Page 73: ...are latched X 011 7 1 Q of HOI i if refresh I refresh 10 1 5 5 1 j I I I L I I 9 2 489 320 mode 1UiCK J U I I 9 8 42 1 U U U U U U U U U V 9 9 62 6 a of HOll L S L mask The following timing relationships are given by forced arrangement Fig 105 S7L I r 0 8 10 8 ns I I OOTCK CAS 1 r xDOTCK 8 4ns miD Figs 106 107 5 8 ...

Page 74: ... I Ad X invalid r I 80 160 t I i 20 80 RAS draw VSHS BLANK ii i So 5 R CS CAS CRAM OP DBD WE X I L ____ _ _ i F 7 2 64 2 CPU I CPU L ________ _ _ _ _ _ J _____________________________________ j F 7 2 45 2 Q of HOO9 IDBINI j j4 6 5 40 a of HO 2 I t 6 3 40 a of HO 3 _ ___________ I t 4 6 3 40 if draw 1 1 9 54 7 I 01 j4 9 54 7 I I 11 57 8 ____ I f 1 57 8 Q of H014 053 DAS MASK G054 CASMASK ___ Ir I I...

Page 75: ... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DiS P I I 1 15 9 792 I CPU A r I j 1 7 86 7 n I L _ _ _ _ _ _ _ _ _ 1 ____ ______ I L ____________ CPU Timing LOAD I I S7 L ll I OOTCK CRL READY r d _ _ _ _ _ _ _ _ _ _ _ _ o iIo IO S 82 9 15 6 89 8 0 j I 11 l_61 L 1 READY wire L J L COl t 8 4 52 7 110 1 1 r CPU command L _ _ _ _ J latch Fig 109 a ...

Page 76: ...EA 1 EA2 EA8 04 04 1 4 I A4 n I tch Fig 109 c VDC1 internal signel LSI66 10 _____________________________________________________________ VDC2 internal signal OA 2 1 A C 2 ot S7L U U U U U j U o spleV dd JV O A C 2 1 O A C 2 V1 E A 1 IIX R A X R A I X EA 2 X E A S X O A X O A VX DA X O A I X O A 2 c r x O A C 2 Display data t om X OA C 2 X X OA I DA I UC X DA C 2 DA Display start address C C R EA ...

Page 77: ...f two bytes with the first byte assigned to a CTRL ALG code and the second byte assigned to the entry code Description of special keys A SHIFT key Used to place the keyboard in the shift mode used with other keys Operation of the SHIFT key alone is invalid no code is transferred to the CPU B CAPS key Used for shift character selection Operative only in the normal mode If used with the SH IFT key s...

Page 78: ...1 The CPU sets STC to one to complete the transfer sequence 77 MZ 5600 Keyboard When STC is set to zero the keyboard reads the result of the parity check When STC is set to one it sets DK to one to enable an interrupt from the CPU and completes the data transfer sequence If a parity error was detected the keyboard terminates the data transfer sequence then tries the same data send again Repeat nin...

Page 79: ...as correct While the search cycle is 5 5ms it is extended to 16 5ms if a bounce occurs KEYl KEY _______ STROBE SAMPLING DATAl _ _ DATA _______ I1 JULJlJLJUl_____________ OUT DATA __________ JfLJl f f u KEY2 DATA Fig 117 Key search sequence for two key operation is the same as that for single key operation_ When two keys are simul taneously pressed key data for the first and second keys are success...

Page 80: ... IN Accepts a quartz signal 6MHz for the internal clock oscillator IN Accepts a quartz signal 6MHz for the internal clock oscillator IN Initialization input of SOC49 IN 5V IN CPU interrupt strobe input STC IN GND N C N C N C N C IN Returns signals from the keyboard IN GND OUT Send data to the System Unit DK OUT Data enable start signal SAK to CPU OUT Enables data send to the mouse CTS N C N C IN 5...

Page 81: ...se of 04 and the current ION flows through when 03 becomes active When 03 turns inactive the current IOFF flows through So by controlling the on off time ratio it 80 produces a stable voltage supply Fig 3 shows the 03 driving circuit 1 When 05 turns active the current ION flows through in the direction shown with the solid line and makes Q3 and Q4 active 2 When 05 turns inactive the current IOFF f...

Page 82: ...ed to create the signal ALARM Figs 8 and 9 The rising edge is delayed at power on by the network composed of R40 and C21 and it is determined by the discharge of C21 R41 R42 and VR3 at power off 7 Adjustments VR1 5V voltage adjustment 5V i 0 02V VR2 12V voltage adjustment 12V i 0 05V VR4 5 V output current adjustment 9 2 AiO 2 A VR3 ALARM adjustment 5ms faster than 5V falling edge 16 3 Troubleshoo...

Page 83: ...ng the wave Connect oscilloscope probes to 06 and 05 06 07 M1 M2 06 form between 06 and VCE VCE and make sure that the waveform 012 010 applies to 01 increase the input voltage appears as shown below 1JL 14 I 28V 20I sec 5 1 Confirm appearance of Adjust the 12V output voltage by means M2 011 VR2 R36 012 010 12V output voltage of VR2 Clockwise turn of the VR2 applies to 01 increases the voltage Sho...

Page 84: ...k ALARM Connect the 5V line to the ALARM pin 08 09 010 07 08 09 C20 in a manner shown below C2l VR3 0 tIN C 5V 1Kn Then there should appear 5 V between OV and ALARM pins Increase the input voltage When the input voltage is slowly increased Do not try to manipulate VR5 to 18 VAC the voltage on this pin changes Use the memory oscilloscope Check if ALARM is 5V from OV to 5V at an input of 15VAC when ...

Page 85: ... occurred it is alerted by a long beep The long beep will sound once for a RAM check error twice for a ROM check error and three times for an MFD check error The pertinent error type will be shown on the display as shown in Fig 4 The details of each error type will be described later Once the error message appears on the screen check execution pauses for five seconds then the screen is cleared and...

Page 86: ... 48 Message Meaning Beep count 10 1 1 1 1 1 1 1 2 2 3 3 3 3 Numeral identified by an asterisk is not correct A16 is repre FEDCBA9876543210 sented by 0 l 30000H Error address on memory 17 3 4 RAM capacity message Table 49 Message Meaning Presently existing RAM capacity if the 128KB displayed value does not agree with the 128KB 256KB or actual capacity the RAM is defective or 512KB an error exists o...

Page 87: ...ay Red B 7 20 GND DATA7 White Red B 8 21 GND DATA8 Yellow Red B 9 22 GND ACK Pink Red B 10 23 GND BUSY Orange Red C 11 24 SRES PE Gray Red C 12 25 SELECT 4 This hole is sometimes blocked off at the Computer 25 way socket If it is remove PIN 13 from the 25 way plug at the Computer end of the Printer lead in any case there is no connection on this pin 86 PRT Side J c5C J I I I I I I II Wire PRT side...

Page 88: ...range Red A 1 3 SEl3 Yellow Red A 7 16 GND Pink Black A 6 4 MOTOR ON Orange Red B 11 17 GND Orange Black B 8 r 5 DIRECTION Gray Red B 13 18 GND Gray Black B 10 6 STEP White Red B 15 19 GND White Black B 12 7 WR DATA Yellow Red B 17 20 GND Yellow Black B 14 8 WR GATE Pink Red B 19 21 GND Pink Black B 16 9 TRACKO Orange Red C 21 22 GND Orange Black C 18 10 NR PR Gray Red C 23 23 GND Gray Black C 20 ...

Page 89: ... B Pin No GND 1 SO 2 RD 3 RS 4 CTS 5 READY GND 7 OR 6 GND CD 8 Cl 22 ER 20 RT 14 1500 50 Open Connection table Pin Wire No color 1 Gray Black B 2 Gray Red B 3 Orange Red B 4 Pink Red A 5 Yellow Red A 6 White Red A 7 Gray Red A 8 Orange Red A 9 N C 10 Orange Black B 11 Pink Black A 12 Yellow Black A 13 White Black A 14 Gray Black A 15 Orange Black A Connector B Pin No Connector Wire color Signal Co...

Page 90: ...256KB l 1 1 IOPTION Z IR ttZ 1R2Z O RAM w256KB IPL RO 16KB PROTECTION lK X 4BIT 11 1 rl 1 SLOT i 1 SLOT Z SLOT I SLOT 4 1 1691T 1 _____________ 1 1 1 STSTEtt I I ttZ 1U05 SLOT 5 I HZ IUO L LLl j BUS 1 SYSTEM ADD BUS 1201 _ _ _ _ _ _ _ _ _ _ _ _ _ J AOSlO L f i2h SYSTEI1 DATA BUS 1161 SYSTEM COttttAND BUS FO H 16632 t JI 11 r I lID COMMAND BUS 11 11 1 illFDC UPD765A r lA S 232C B 1 EQUIPED STAND D ...

Page 91: ...Ln mN 1 luul I I I J VI I l VI Cl Vl Vl C Cl 0 C J QI U U If N EE __ L c 1 1 C Cl 0 Cl 0 lfI N _ co 0 Cl r 10 11 _ O t D r l O l l l 2 til I o _ N m LI I r OOOOOOOQ IC Q Nm I QOoQOOOOO C C c c C C C r I _ co NI I N O IOO N In 0 r u Cl Cl Q It DC et QI It IIIr U Z _ _ _ _ l J w u ...

Page 92: ...014 2 D S S IS ff015 iilml I M Mt RAn I7 ASI m 12 Hll A I1 H3 AI I1 H3 11 H31 AZ BRln Z AS E Jl iiR 12 A51 CAD POIOZ A A IKX8 r S Al 00 AX1 100 RIO AX2 00 Al3 Al AlS U6 AX B c SYSTEM BOARD AXZ 15 An 51 AZ AS AS AS A7 NU o llL W v 1 t I 3 il v m Hf Im 01 DO 21 AXO 5 At AXI AI LSOO NU LS20 D T ROM RAM 64KXl ORA I I I I 4164 OR I E T n F 6 A 11 A4 10 13 A5 iE m15 rn 01 DO c 12 14 I I I I I I I I I I ...

Page 93: ... I Z H3J IS UI 15 31 I7 ASJ I c ...

Page 94: ... L _ _ _ _ ___ J 14 H4 8 1 E 10 r 14 H41 lAI CSPIO 5189 12 H51 A2 R34 L m 9 6 CSCTC _ TO cJ NU lOO 1 Cl0 5 lE 75189 I C 4 R H E i 13 14 H61 t G 1B Y1 J NU 6 16 T 220P T C I I 13 10 CS PC2 rtr 7fT 220P I GHQ IDO r 14 RI29 RESET 35 RESET PB5 23 CN4 1 23 4 H3 16 A3 17 A51 IDl lOO 12 IEl 11 RESET lORD 5 RD 24 11 OG 0 t sru I INT 4J IOWR 36 PB6 CN4 24 I IS szS CKITGO R121 RI25 3F PCS 2 I OF 2 L f 4 0 6...

Page 95: ...C 4C 3 Z11 u l l u r F Cl no WINDOW 2 i G F H I FSHi t LS A r OOP 11 j _Ill mm _ mm C 30Ir f N _ l _ 10 TC F J H 00 1 L J r 100 _ I 11 I OACHI 1 11 15 0ACK SYNC I 1 A r 8CLH LS 7ft I 1 I I i m J l r C 5 _ C Z5114 HZI U __ 1_ V_ LS12 5i JI2K 143 I i j l o f 1 c _ I II 11 r r L 0 4 H31 5 A21 7 SI D D D5 I 101 13 UPD 05 i r 5 1 I J I DE m H II F 00 L INDEX 35 K I I I 1 1 _ _ DIHECTION 37 J j I z 3 I ...

Page 96: ... 9 A a l l P03 10 ISG IICNIZ 8 8 9 8 V B CNIO 8 I I CNI BI5 CLK86 1 ClK805 1 4 HII t 19 I L _______ J V L ________ I 1 CLK 1 Cl _ LS245 0 G LSOO 7i 7404 X 6 6 I CNI AI4 m f ost 1 6 AZI lZ HIJ MROC I BO 2 t _ 1 CNI 814 4 RSf5i RSTSV I Z A61 A VC 2 JI7F lR I9f L I CNI AIS 4 I 1 2 A31 12 H1J I LS305i IA 7 LS36i MAO CNI A3 J RAMINH LS08 BI 4 5 I MAl f I IAI 12 A1J 13 All I MAZ CN1 B31 13 A1I 9 BZ 6 9F...

Page 97: ...9 i1fl m 13 OND 30 mm OND 31 IfR PR I CAD P008e IS OND 2 IIDDiTI OND ml 11 OND REm A B C D CPU BOARD CONNECTOR cv EX MFD 1 Ili6li 2 ffil IS SUi SEL3 iilmIlf1ii1 S IiTmTTl N 11 mP OND 1 iIf1j ffi ND iif Cil 20 OND mm 21 ND 10 iln 1I 22 OND 1 11 RO OUA 2 OND 12 ml 24 GNO 13 moT s 0 PRINTER 1 mroR 2 DATAl OND DATAl ND DATA OND DATA 11 OND DATAS OND 1 OAlA6 GND DATA1 20 GND DATAe Z1 OND 10 m 2 GND I 1...

Page 98: ......

Page 99: ... 100 2XCCLK AOl5 31 AOl5 r YAO All lXCCLI 1 07220 v YA I I3 AlI RA4 330K 2X OACI VCC GNO r V VAZ I3 AlI 43 l ll ADO CLI JIO ADO 11 9 VOO I V VAl 13 AlI IAO 5v IAI 44 J AOI AOl lZ 8 VOI St v VU 13 Atl IAZ 45 i AD2 AOZ 13 7 V02 v VA513 AZI IA3 46 I J I A03 A03 14 6 V03 V VA6 13 AlI IA4 41 J A04 _ 10 A04 IS B ZG A 5 V AI V VA7 3 AI IA5 48 i J ADS O Qf2 ADS 16 4 V05 51 I J I A06 8A A06 11 3 V06 r VAI6...

Page 100: ...34 16 Bl GHD Jl ___ C 4 ___ _ I IiND GNO 7lT 5mi K _I _ H5Y _ I l5125 Dft SA lS04 LSlse 1 1 n j i I __ J 1 14 AI RA VA 13 A2 Re WB 10 3A 15 DB A f l Q 1 01 16 Q2 le 03 Gi 11 DZ I D D1OI LS670 n 50 OF VDCl cs IiiSO G H R fi1JI A4 1 19 R13 8 lOO un u R 5 RAn 1ffi 3 UJ lOO ii S 4 ill 10 RI7 i5l13 A3J 2 6 ifiSf 11 1G 100 r I 15 Ii n 1 5 1 I i T RASS 13 1 5244 DD L r liNO 13 L_ vet 36 5Y iDli 15 V6li 1...

Page 101: ...D 14 In I D I _ I 1013 7 D 1 3 1 VD 12 I D I 2_ I 1011 5 ROll VDlD t Dilt 109 1 3 D __ VD 1 2 D __ VD7 _ D 7__ VD6 In I D __ VDS J 7 D 5_ VD I D __ VD3 5 R03 VD2 t D 2 VDI f 3 D I__ 1 100 r2_ D _J 13 I 12 Q Q go _ _ 1 z r X tD _ r Q r c N lE r Ir r v v Ir r v v J J J J J r r r r i t i t r r r r r v v r v v v v IJ I I IJ r r r r r r r z r x r t X t t t r r v t J I I IJ N MZ 5600 CN BDO BDl N HBDZ N...

Page 102: ...RD CN QCNCn 021 CZZ vce 15 11 Ice IsYI Ice 15 11 3Z I Ice ISV vce 5 1 33 I Ice 15 11 Run 41 imR om 35 I I1IR iIVlr I J1Iif iiiil 371 IiITA 11 f6m DO I D 10 D2 40 I 03 11 D4 I DS 2 D 421 01 131 01 431 09 141 010 441 011 151 012 451 013 16 I DU 461 D S 111 GNO I riND 11 GNO 41 liNO 191 GNO 491 IiIr 20 I AO 5 1 AI 21 I AZ s 1 u 22 I 521 AS 23 I A6 ss I A7 24 I All 541 A9 25 I AI 551 All 261 A12 561 A...

Page 103: ... lIIl 5600 ...

Page 104: ......

Page 105: ...XI DIO D DI D7 D6 DS D D Dl DI S 1518L1X16 I U 11 II 14 IS 17 11 XIS X14 X13 Xll Xli xu XI X7 x X5 U X XI XI vce 5W ND G Kur I T7 T6 T5 T4 5 U TZ 7 T1 I TO CArs KAICA 11 GItA 1Z ROW lIt 13 K5 14 K o I 2 8 4EEr7T 8 I 9 10 I II 72 I 78 I I 82 I 88 I 84 I 85 I 12 26 74 75 86 87 88 89 40 76 77 90 91 92 98 41 78 94 95 96 97 67 79 80 98 99 100 101 81 102 108 104 MZIKll I 88 1 9 only EJ with LED D F F H ...

Page 106: ... loIl S600 ...

Page 107: ... 4 V2 RC _____ 1 ST 7D I I lr L ________ _ STI DB bA 114 11 0 STII 01SOY 0000 ST22 1142 2 _ 1143 2 2I D Q3 RJ R7 R 5So I I ZW lie Q 11 6 110 C2 I R4 330 I 1 3 1N 1 T T 330 C4 I 1 0 0 tD4 1 LI RIO 560D AAA III R240 0 D AAA _ _ R23 IDOD 5 11 0 IJC in ic O1l O1 o cs 4 R I5ICD r 8 11 9 10 R2S 22fl 010 1128 lOO 1L R27 2 _ I 4 7KO R48 Y W lKO Ql1 R36 0 6110 211 R4S I 1 IU U T o C 5 R38 R30 C 4 D 5 B CD ...

Page 108: ......

Page 109: ...1 IZ 13 14 S t7 11 zo 2 21 Z 2S 21 27 ZI 1 12 I IS 17 Z GND ____ 3_ A B yee 1 5Yl yee SVI YGG 1 12Y GNO GND yee 1 5YJ vee I SYI I1I n 1r fi R n 6Am mRl iiffi m eLKI6 GND irn TaR tm ilm TI m 0 DI DS D7 D DII DI3 D S GND A IRl A A AS A7 All A I A S A17 AtO GND B c D E F G H I MZ1U05 MOTHER BOARD 6 5 SLOTI ICNII A SLOT ICN3 A 01 10 I 101 101 4 8 8 SlOTl CHZ A A SLOT4 ICN4J 01 10 0 1 _ 2oJ 84 8 84 8 3...

Page 110: ......

Page 111: ... SYJ II ft IT l4 10 nr n 11 miil IZ I Im 3 mR1 14 a IS elK 16 GNO 17 rm I1I1IE 19 lm 0 rnIil ZI ram zz DI n D DS S D7 Z6 D Z7 DII ZI Df3 DIS Sf AI JZ IiIl al 54 A3 s A7 37 3i 11 40 AI 41 11 4 AI D PAIITS SIDE f I 8 I c I D I E I F G 1 H MZ1UD7 MDTDER BOARD MADE IN JAPAN UVWXYZ MZ IU07 SLOTI SLOT3 1 Ji43 40 30 _ 843 u SLOTS MS 40 SO to It SLOT2 GC Nc Wl023ACZZXS M S L O T I so 10 MOTHER BOARD NlQ5I...

Page 112: ... iIIZ 5600 ...

Page 113: ...IR G r 7 5 J 330 I I SA lSOO 828 16 013 013 IA28 15 012 D 1827 se 14 011 DI1 21 13 010 010 I 1 9 1 126 LSZ45 12 D9 tAZ 11 08 08 7 C 00 LS32 R 100 L f DI DO u 0 n14 e I IB25 18 01 D7 IF j Ius 17 Dj D6 e 3D 7 t r3 CS32 I I L 5 1 1 19 100 05 11 24 15 04 D CAS 01 DD DI DO 2E 0 01 DO u 0 nu ID lE DI DO F 01 DO 01 DO U 10 02 nu lE 3 01 DD 01 DO DJ 00 20 2H 64KXI ORA 64KXI DRAM 0 01 DO 01 DO U 11 U 12 03...

Page 114: ......

Page 115: ...12 13 NU AMWC T2 13 NU 14 1 TI 15 NU TO NU AI8 MRDC lLS138 MAl LSDO 1 I 1 A32 3 12 tIl VI 7 SV MAl I 5G Y f 11 I I 831 lJ J5G 6 31 MAO I 1 ZG 2 lS32 LS32 t 1 n M4 1 SHE I lS14 I I 2 5 VHICX 101111 MS ID AS B32 I I L IJ 4G J 2 6 A 14 j i IDS 106 2 14 i _ 14 Z i 14 2 H 2 14 n l 4 n l 4 00 01 t DO 1 DJ ba 01 D I 01 00 01 DO of DO IC 2C C C SC 6C 7C 641 XI ORAfl I I LSOO I I 1 10 3 A7 I 19 1 33 WE 015...

Page 116: ... JoIZ 600 ...

Page 117: ... l l l l l l l l D Ut 01 I I VAD I DO 01 DZ 03 VAt 13 AD f f VA2 12 AI t f VA 11 f f vu 8 t 1 16KX4 f VAS 1 f VAI 5 DIU f vu 10 f S r n f f if I J t K t L IG f f m m m m I r c 4 l rrJ 1 1 1 13 l l l l l l l l S 3 VA DO 01 DZ DS VAI 13 f f LS244 VAZ It 1 t r G 16 R3 100 ui 11 2 f I if 11 3 R2 100 VA U r r VAS 1 U 16KX4 I I mr I RS 100 S r r rnH RI 100 VA ORA I I 2 T IO vu m 5 S R r r IWl Srn I I 13...

Page 118: ... lZ 56O l ...

Page 119: ...1 C N W j U1 a l MACe CJ la ZA 1 0 40 A33 _ N W co 0 _ _ U1 a l 0 0 0 0 0 0 0 10 IU At 1 AD 6 7 AD l l l l J J l l J L LJ lL lL L L lA I A20 l1fi t 12 I J ORe 8 6 517 2 I 15 8 2 6 17 I 2 5 6 7 8 9 I I I 1 5257 J 1f j J 5 Ir lA8 8 A18 AMWC 2 A Y 3 JAM we LS24it U er ZA9 39 AIO 818 Alowe 14 JAlowe I D G nG J h O I G 1 1 lW V 820 I G G D _ T y G 19 3E T f9 20 _e _atl9 8 6 800 m d s y T l r l A 6 36 I...

Page 120: ......

Page 121: ...MZ 5600 PARTS LIST GUIDE ...

Page 122: ...QCNCM1026ACZZ AK C Connector 34pin 38 LHLDW2334RCZZ AC C Wire holder MZ5631 39 DUNT 1182ACZZ E CRT PWB unit Ref block 2 41 QCNCM1025ACZZ AK C Connector 34pin 42 LSUPPI002ACZZ AC C Spacer 43 QCNCMI024ACZZ AP C Connector 60pin 44 QCNCW0207HCZZ AK C Connector 8pin 45 LSUPPI00IACZZ AB C Spacer 46 XBPSD40PI0KSO AA C Screw 4XI0KS 47 V S P 0 0 8 0 P 6 0 8 N AN B Speaker P008P 48 PCUSGI006ACZZ A B C Rubbe...

Page 123: ...rn Exteries PARTS CODE NO 77AC ZZ7 11 D DUNT 1309FCZZ L B N D J 0 7 0 A C Z Z l 1 7 i L DUNTKl L I DESCRIPTION 64 2 MZ5600 MZ5645 2 MZ5631 70 ...

Page 124: ... IC 74LS166 35 VH S N 7 4 L S 2 5 7 N AG B IC SN74LS257N 36 VH SN74S74N 1 AF B IC SN74S74N 37 VH SN7400N 1 AG B IC SN7400 38 VH SN7404N 1 AF B IC SN7404N 39 VH S P 6 1 0 2 C 0 3 4 BA N B IC SP6102C034 40 VH S P 6 1 0 2 C 0 3 5 BA N B IC SP6102C035 41 VH TMS4416 1 5 AZ N B IC TMS4416 42 VH UPD7220D 1 BS B LSI UPD7220D 44 VRD ST2EY101J AA C Resistor l 4W 1000 5 45 VRD ST2EY10 3J AA C Resistor l 4W 1...

Page 125: ...r 50WV 120PF 58 VCKYPU1HB221K AB C Caoacitor 50WV 220pF 59 VCKYPU1HB222K AA C Capacitor 50WV 2200pF 60 VCKYPU1HB561K AA C CapaCitor 50WV 560pF 61 VCKYPU1HB681K AA C Capacitor 50WV 680PF 62 VCKYPU1HB682K AA C Capacitor 50WV 6800pF 63 VCQSTT2TS271J AD C Capacitor 150WV 270PF 64 VCQYKU1HM102K AA C Capacitor 50WV O OOluF 65 VCQYKU1HM152K AA C Capacitor 50WV 1500pF 66 VCQYKU1HM333K AB C CapaCitor 50WV ...

Page 126: ...9 VRD S T 2 E Y 3 3 3 J AA C Resistor 1 4W 33KO 50 140 VRD S T 2 E Y 3 9 2 J AA C Resistor 1 4W 3 9KO 5 141 VRD S T 2 E Y 4 7 1 J AA C Resistor 1 4W 4700 59i 142 VRD S T 2 E Y 4 7 2 J AA C Resistor lj4W 4 7KO 5 143 VRD S T 2 E Y 4 7 3 J AA C Resistor 1 4W 47KO 5 144 VRD S T 2 E Y 5 6 1 J AA C Resistor 1 4W 5600 5 145 VRD S T 2 E Y 1 8 3 J AA C Resistor 1 4W 18KO 5 146 VRD ST2EY563J AA C Resistor 1...

Page 127: ...1 AB B Diode DS1588L2 14 VHiM74LS05 1 AE B IC M74LS05 15 VHiM74LS14 1 AM B IC M74LS14P 16 VHiTC4514BP 1 AN B IC TC4514BP 17 VHi8749 AC31 BS N B IC 8749 18 VRD ST2EY100J AA C Resistor 1 4W 100 5 19 VRD ST2EY101J AA C Resistor 1 4W 1000 5 20 VRD ST2EY102J AA C Resistor 1 4W 1KO 5 21 VRD ST2EY104J AA C Resistor 1 4W 100KO 5 22 VRD ST2EY121J AA C Resistor 1 4W 1200 59 23 VRD ST2EY222J AA C Resistor 1 ...

Page 128: ...KF015A AB C Terminal 125 00P24KC015N AD C Spacer 126 00P21KCOOBA AK N C Lever 3 ExcE P t EnglistIL 150 VHD1S2075K 1 AB 8 Diodecl1 S207SKl 201 o0 P C 5 K C 0 8 3 0 0 1 AK N C Key top 202 o0 P C 5 K C 0 8 3 002 AK N C Key top 203 o0 P C 5 K C 0 8 3 003 AK N C Key top 204 o0 P C 5 K C 0 8 3 004 AK N C Key top 205 o0 P C 5 K C 0 8 3 0 0 5 AK N C Key top 206 o0 P C 5 K C 0 8 3 0 0 6 AK N C Key top 207 ...

Page 129: ...N C K tQQ 248 o0 P 8 6 N3 C 5 2 0 0 6 AK N C K tQQ 249 o0 P 8 6 N3 C 5 2 0 0 7 AK N C K tQQ 250 o0 P 8 6 N3 C 5 2 0 0 8 AK N C K tQQ 251 o0 P 8 6 N3 C 5 2 0 0 9 AK N C Key top o0 P 8 6 N3 C 5 2 0 2 2 AK N C Key top French 252 o0 P 8 6 N3 C 5 2 0 1 8 AK N C Key top Germany o0 P 8 6 N3 C 5 2 0 1 5 AK N C Key top English o0 P 8 6 N3 C 5 2 048 AK N C Key top French 253 o0 P 8 6 N 3 C 5 2 0 1 9 AK N C ...

Page 130: ... 8 6 P 6 C 5 2 0 0 1 AK N C Key top 296 o0 P 8 6 N 3 C 5 2 0 1 4 AK N C Key top 297 o0 P 8 6 N 3 C 4 1 097 AK N C Key top 298 o0 P 8 6 N 4 C 5 2 0 1 1 AK N C Key top 299 o0 P 8 6 N 4 C 5 2 0 1 2 AK N C Key top 300 o0 P 8 6 N 4 C 5 2 0 1 3 AK N C Key top 301 o0 P 8 1 U 5 C 4 100 1 AQ N C Key top 302 o0 P 8 6 N 5 C 5 2 001 AK N C Key top 303 o0 P 8 6 N 5 C 5 2 002 AK N C Key to 304 o0 P 8 6 N 5 C 5 ...

Page 131: ... 201 1 202 1 203 1 204 1 205 1 206 1 207 1 208 1 209 1 210 1 2111 2721 273 1 282 1 283 1 2841 2851 2741 275 1 286 1 287 1 288 1 289 1 276 1 2771 291 1 292 1 293 1 278 1 295 1 296 1 297 1 279 1 280 1 300 301 281 1 304 Figure means refer number on the parts list 10 ...

Page 132: ...40 08100 AA 24 NFANP1006ACZZ BG 100 QCNCM2191SCZZ AG 101 QFS A1002CCZZ AE 102 QFSHA1002CCZZ AB 103 RC CZ1002ACZZ AD N 104 RC i L F 1 0 0 1 AC Z Z AH N 105 VCE9HE2EP104K AK N 4 j 13 PART RANK C C D C C C C C E C C B C D C C B C C C C C C B A C C C C DESCRIPTION Screw 3X5 Earth terminal AC switchpanel Earth wire Soacer AC socket CM3 Screw 3X6 PWB angle Power supply PR1 unit 200V Lead wire Lead wire ...

Page 133: ...120618 AD C Capacitor 50F2S104K CI5C23C25 127 0 AE30170008 AF C Capacitor 25UL8330 M C16 C17 C24 128 OAE30182562 AD C Capacitor 50ULB22 M C19 C21 C2B 129 OAE30169640 AC N C Capacitor 50ULB4R7 N C20 130 OAE30120540 AC C Capacitor 50F2S333K C26 131 OAE30569554 AC C Capacitor MR25 6 BHM G Rl 132 VRD ST2EY392J AA C Resistor CR25 3 9KO J F R2 133 VRD ST2EY101J AA C Resistor CR25 1000 J F R3 R23 134 OAE...

Page 134: ...DESCRIPTION 6 14 13 ...

Page 135: ...XUPSD30P10000 AA XBPSD40P08KOO AA XBPSD30P06000 AA XWHSD30 0S080 AA XBBSC30P06000 AA Unit DUNT 1341ACZZ BU 10 4 l NEW PART DESCRIPTION MARK RANK C Expantion cover C Expantion cover D Expantion box C Connector 86pin E Mother board PWB unit C Insulator C Screw 3 X 10KS C Guide holder C Screw 3X10 C Screw 4X8K C Screw 3 X 6S SW C Washer 3HW C Screw 3X6 E Expantion unit for Ex Except Europe 2 8 14 MZ5...

Page 136: ...10 I DESCRIPTION 15 5 6 ...

Page 137: ... 3 VCEAAUICW476Q AB C Capacitor 16WV 47pF 4 VCTYPU1NX104M AB C Capacitor 12WV 0 10pF 5 VHiCX101 1 AU B IC CX10l 6 VHiM74LSOO 1 AE B IC M74LSOOP 7 VHiM74LS138 1 AK B IC M74LSl38P 8 VHiM74LS14 1 AM B IC M74LS14Pl 9 VHiM74L5158 1 AG B IC M74LS15SP 10 VHiM74LS20 1 AE B IC M74LS20P 11 VHiM74L5245 1 AM B IC M74LS245P 12 VHiM74LS257 1 AQ B IC M74LS257P 13 VHiM74LS32 1 AF B IC M74LS32P 14 VHi4164 1 5 0 H ...

Page 138: ... 4 1 AE N C GSTN 1015ACZA 5 15 AF N C 1 5 10 AE N C H QCNCWI008AC05 1 50 AB B HBDGBI002ACZZ 1 72 AD C QCNCWI017ACZZ 1 33 AF C 1 5 5 AD C 1 3 6 AF C HPNLCI002ACZA 1 9 AL N D QCNCWl 018 ACZZ 4 3 AF C HPNLCI006ACZZ 6 15 AE D 1 5 7 AF C HPNLCI007ACZZ 6 4 AN D QCNCWI021ACZZ 1 28 AS C J 1 3 7 AS C JBTN I00IACZA 1 54 AB C QCNCWI022ACZZ 1 31 AU C JKNBPI006ACZA 1 71 AD C 1 3 8 AU C L QCNCWI023ACZZ 1 29 AT ...

Page 139: ...D C RVR Q1001ACZZ 3 36 A F B VCQYKU1HM102K 3 64 AA C S VCQYKUIHM152K 3 65 AA C SPAKA1004ACZZ 5 402 AS 0 VCQYKU1HM333K 3 66 AB C SPAKA1009ACZZ 5 403 AB o VCQYKU1HM472K 3 67 AA C SPAKA1270ACZZ 12 7 AE N VCQYKU1HM682K 3 68 AB C SPAKA1368ACZZ 10 1 BD VCTYPU lEX4 72F 3 129 AA C SPAKA1408ACZZ 10 2 AY o VCTYPU1NX104M 2 16 AB C SPAKA1413ACZZ 5 404 AD N o It 3 69 AB C SPAKA1462ACZZ 11 18 AG o It 4 12 AB C ...

Page 140: ...RD ST2EY473J 3 143 AA C VHiNE555 1 3 110 AG B VRD ST2EY511J 7 155 AA C VH i RP5CO 1 1 3 111 AV B V RD S T 2E Y 5 6 1 J 3 144 AA C VHiSN74LSOO 1 3 112 AE B 1 7 139 AA C VHiSN74LS122N 2 33 AH B VRD ST2EY562J 7 145 AA N C VHiSN74LS166N 2 34 AN B VRD ST2EY563J 3 146 AA C VHiSN74LS21 1 3 98 AE B V RD S T 2E Y 6 8 1 J 4 26 AA C VHiSN74LS257N 2 35 AG B 7 152 AA C VHiSN74LS541N 3 113 AP B VRD ST2EY682J 3 ...

Page 141: ...5 101 AH B 0 1 00PKCLl1901 Z 5 116 AP N B OAE10432908 7 4 AE C 00PKCLl1902 Z 5 116 AL N B OAE10447100 7 5 AE C 00P08KC275B 5 104 BK N C OAE10447113 7 9 AC C 00P08KC392A 5 104 BK N C OAE10452973 7 51 AK N C 00P13KF015A 5 124 AB C OAE10453026 7 11 AD N C 00P16KC004A 5 105 AG C OAE10480387 7 12 AE C 00P16KF006A 5 106 AG C OAE10566366 7 8 AC C 00P19KC003A 5 107 AE C OAE10646435 7 3 BK N C 00P21KC005A ...

Page 142: ...215 AK N C 00P86N5C52003 5 304 AK N C 00P86NIC52078 5 221 AK N C 00P86P6C52001 5 295 AK N C 00P86N2C41001 5 276 AK N C 00P86P7C41000 5 282 AK N C 00P86N2C41002 5 277 AK N C 1 5 283 AK N C 00P86N2C41003 5 293 AK N C 1 5 284 AK N C 00P86N2C52001 5 228 AK N C 1 5 285 AK N C 00P86N2C52002 5 229 AK N C 00P86N2C52003 5 230 AK N C 00P86N2C52004 5 231 AK N C 00P86N2C52005 5 232 AK N C 00P86N2C52006 5 233 ...

Page 143: ... SHARP CORPORATION Industrial Instruments Group Reliability Ouality Control Department Yamatokoriyama Nara 639 11 Japan 1984 July Printed In Japan ...

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