National Semiconductor DP83816AVNG Manual Download

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DP83816

DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and

Physical Layer (MacPhyter-II)

Literature Number: SNLS164D

Summary of Contents for DP83816AVNG

Page 1: ...DP83816 DP83816 10 100 Mb s Integrated PCI Ethernet Media Access Controller and Physical Layer MacPhyter II Literature Number SNLS164D...

Page 2: ...ow including directed packets Magic Packet VLAN packets ARP packets pattern match packets and Phy status change Clkrun function for PCI Mobile Design Guide Virtual LAN VLAN and long frame support Supp...

Page 3: ...ion Identification Register 30 4 1 2 Configuration Command and Status Register 31 4 1 3 Configuration Revision ID Register 32 4 1 4 Configuration Latency Timer Register 33 4 1 5 Configuration I O Base...

Page 4: ...ical Layer Block Diagram 15 Figure 3 5 LED Loading Example 17 Figure 3 6 100BASE TX Transmit Block Diagram 19 Figure 3 7 Binary to MLT 3 conversion 20 Figure 3 8 100 M bs Receive Block Diagram 22 Figu...

Page 5: ...D10 AD9 VSS AD8 AD19 AD20 AD21 AD22 AD23 IDSEL VSS PCIVDD NC PCIVDD NC VSS PCIVDD CBEN3 AD24 AD25 AD26 CBEN0 VSS AUXVDD RESERVED VREF PCIVDD AD29 AD31 VSS REQN GNTN RSTN INTAN AD28 PCICLK AD30 PMEN CL...

Page 6: ...t is de asserted before the transaction is in its final phase As a target the device monitors this signal before decoding the address to check if the current transaction is addressed to it GNTN 63 I G...

Page 7: ...ower Management Event Clock Run Function This pin is a dual function pin The function of this pin is determined by the CLKRUN_EN bit 0 of the CLKRUN Control and Status register CCSR Default operation...

Page 8: ...access these signals become part of the ROM address RXDV MA11 15 I O Receive Data Valid Indicates that the external PMD is presenting recovered and decoded nibbles on the RXD signals and that RXCLK i...

Page 9: ...ulses for Auto Negotiation purposes 100BASE TX Reception of ANSI X3T12 compliant scrambled MLT 3 data The DP83816 will automatically configure this common input buffer to accept the proper signal type...

Page 10: ...duration of approximately 50 ms LED100N MA2 144 O 100 Mb s Link This pin is an output indicating the 100 Mb s Link status This pin is driven low to indicate Good Link status for 100 Mb s operation and...

Page 11: ...6 37 84 85 124 125 126 No Connect RESERVED 41 50 127 These pins are reserved and cannot be connected to any external logic or net REGEN 48 Reserved and cannot be connected to any external logic or net...

Page 12: ...ngle port version of the 3 3V DsPhyterII Internal memory consists of one 0 5 KB and two 2 KB SRAM blocks Figure 3 1 DP83816 Functional Block Diagram MAC BIU Interface SRAM 25 MHz Clk MII RX MII TX MII...

Page 13: ...lude configuration control serial EEPROM access with auto configuration load interrupt control power management control with support for PME or CLKRUN function 3 1 1 1 Byte Ordering The DP83816 can be...

Page 14: ...gure the DP83816 to maximize efficiency Architecture of the specific system s buffer memory as well as the nature of network traffic will determine the most suitable configuration of packet descriptor...

Page 15: ...external EEPROM The EEPROM interface provides the ability for the DP83816 to read from and write data to an external serial EEPROM device The DP83816 will auto load values from the EEPROM to certain f...

Page 16: ...B 5B DECODER DESCRAMBLER SERIAL TO PARALLEL NRZI TO NRZ DECODER MLT 3 TO 10 100 COMMON AUTO NEGOTIATION STATE MACHINE FAR END FAULT STATE MACHINE REGISTERS AUTO 100BASE X 10BASE T MII BASIC MODE PCS C...

Page 17: ...R bit 13 controls switching between 10 Mb s or 100 Mb s operation and the Duplex Mode bit bit 8 controls switching between full duplex operation and half duplex operation The Speed Selection and Duple...

Page 18: ...tely 2 3 seconds to complete In addition Auto Negotiation with next page should take approximately 2 3 seconds to complete depending on the number of next pages sent Refer to Clause 28 of the IEEE 802...

Page 19: ...f the PHY Status Register C0h While in Loopback mode the data will not be transmitted onto the media This is true for either 10 Mb s as well as 100 Mb s data In 100BASE TX Loopback mode the data is ro...

Page 20: ...inuously injects IDLEs into the transmit data stream until the next transmit packet is detected re assertion of Transmit Enable 3 9 2 Scrambler The scrambler is required to control the radiated emissi...

Page 21: ...ich converts the voltage to current and alternately drives either side of the transmit transformer primary winding resulting in a minimal current 20 mA max MLT 3 signal Refer to Figure 3 7 Figure 3 7...

Page 22: ...It accepts TP PMD compliant waveforms directly requiring only a 100 termination plus a simple 1 1 transformer The DP83816 is completely ANSI TP PMD compliant and includes Base Line Wander BLW compensa...

Page 23: ...B BP_SCR BP_RX CLOCK MUX MUX 4B 5B DECODER SERIAL TO CODE GROUP MUX DESCRAMBLER NRZI TO NRZ MLT 3 TO BINARY DIGITAL CLOCK LINK INTEGRITY RX_DATA VALID AGC INPUT BLW ADC SIGNAL COMPENSATION ADAPTIVE EQ...

Page 24: ...tage This comparison would indicate the amount of equalization to use Although this scheme is used successfully on the DP83223V twister it is sensitive to transformer mismatch resistor variation and p...

Page 25: ...pected register value based on a known cable length would indicate that the signal quality has deviated from the expected nominal case 3 10 5 MLT 3 to NRZI Decoder The DP83816 decodes the MLT 3 inform...

Page 26: ...nection with good signal integrity If the line state monitor does not recognize sufficient unscrambled IDLE code groups within the 722 s period the entire de scrambler will be forced out of the curren...

Page 27: ...typically three preamble bits at the beginning of each packet Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that...

Page 28: ...arate a Manchester encoded data stream into internal clock signals and data The differential input must be externally terminated with a differential 100 termination network to accommodate UTP cable Th...

Page 29: ...DIO provides the PHY s with a sequence that can be used to establish synchronization This preamble may be generated either by driving MDIO high for 32 consecutive MDC clock cycles or by simply allowin...

Page 30: ...in 10 Mb s mode when a collision is detected the collision is not reported until seven bits have been received while in the collision state This prevents a collision being reported incorrectly due to...

Page 31: ...Configuration Latency Timer Register RO 10h CFGIOA Configuration IO Base Address Register R W 14h CFGMA Configuration Memory Address Register R W 18h 28h Reserved reads return zero 2Ch CFGSID Configur...

Page 32: ...be set to 01 indicating that DP83816 supports medium DEVSELN timing 24 DPD Data Parity Detected Refer to the description in the PCI V2 2 specification 23 FBB Fast Back to Back Capable DP83816 will set...

Page 33: ...5 3 Unused reads return 0 2 BMEN Bus Master Enable When set DP83816 is allowed to act as a PCI bus master When reset DP83816 is prohibited from acting as a PCI bus master 1 MSEN Memory Space Address...

Page 34: ...t 00000000h Offset 0Ch Access Read Write Soft Reset Unchanged Bit Bit Name Description 31 BISTCAP BIST Capable Reads will always return 0 30 BISTEN BIST Enable Reads will return a 0 writes are ignored...

Page 35: ...d Bit Bit Name Description 31 12 MEMBASE Memory Base Address This is set by software to the base address for the Operational Register Map 11 4 MEMSIZE Memory Size These bits return 0 which indicates t...

Page 36: ...nly 10 1 unused reads return 0 0 ROMEN ROM Enable This is used by the PCI BIOS to enable accesses to boot ROM This allows the DP83816 to share the address decode logic between the boot ROM and itself...

Page 37: ...ant The DP83816 desired setting for Minimum Grant The DP83816 will initialize this field to 11d 2 75 sec The value in this register can be loaded from the EEPROM 15 8 IPIN Interrupt Pin Read Only alwa...

Page 38: ...icate PCI clock not needed for PMEN 18 16 PMV Power Management Version This bit field indicates compliance to a specific PM specification rev level Currently set to 010b 15 8 NLIPTR Next List Item Poi...

Page 39: ...e Control Status Register R W 48h RFCR Receive Filter Match Control Register R W 4Ch RFDR Receive Filter Match Data Register R W 50h BRAR Boot ROM Address R W 54h BRDR Boot ROM Data R W 58h SRR Silico...

Page 40: ...mit Reset When set to a 1 this bit causes the current transmission to be aborted the transmit data and status FIFOs to be flushed and the transmit state machine to enter the idle state TXE goes to 0 T...

Page 41: ...configuration control bits 17 PINT_ACEN Phy Interrupt Auto Clear Enable When set to a 1 this bit allows the phy interrupt source to be automatically cleared whenever the ISR is read When this bit is...

Page 42: ...fault allows normal transmitter back off operation R W 5 POW Program Out of Window Timer This bit controls when the Out of Window collision timer begins counting its 512 bit slot time A 0 causes the t...

Page 43: ...MDIO pin R W 4 MDIO MII Management Data Software access to the MDIO pin see MDDIR above R W 3 EESEL EEPROM Chip Select Controls the value of the EESEL pin When set the EESEL pin is 1 when clear the E...

Page 44: ...Setting this bit to 1 allows the SRAM BIST engine to be reset R W 9 8 Reserved for NSC internal use only Must be written as a 00 otherwise R W 7 RBIST_EN SRAM BIST Enable Setting this bit to 1 starts...

Page 45: ...SSERR Signaled System Error The DP83816 signaled a system error on the PCI bus 21 RMABT Received Master Abort The DP83816 received a master abort generated as a result of target not responding 20 RTAB...

Page 46: ...al Rx Drain Threshold has been met by the incoming packet and the transfer of the number of bytes specified by the DRTH field in the RXCFG register has been completed by the receive DMA engine This in...

Page 47: ...s 0 the corresponding bit in the ISR will not cause an interrupt 9 TXIDLE Tx Idle When this bit is 0 the corresponding bit in the ISR will not cause an interrupt 8 TXERR Tx Packet Error When this bit...

Page 48: ...abled When set to 0 the hardware INTR signal will be masked and no interrupts will be generated The setting of this bit has no effect on the ISR or IMR This provides the ability to disable the hardwar...

Page 49: ...h Access Read Write Soft Reset 00040102h Bit Bit Name Description 31 CSI Carrier Sense Ignore Setting this bit to 1 causes the transmitter to ignore carrier sense activity which inhibits reporting of...

Page 50: ...it words 64 bytes 110 32 32 bit words 128 bytes 111 64 32 bit words 256 bytes NOTE The MXDMA setting value MUST not be greater than the TXCFG FLTH Tx Fill Threshold value 19 unused 18 Reserved for NSC...

Page 51: ...ive descriptor is NULL signifying the end of the list RXDP will not advance but will remain on the current descriptor Any subsequent writes to the RXE bit of the CR register will cause the receive sta...

Page 52: ...l transmission such as during a PMD loopback or full duplex operation will be accepted as valid received data Additionally when set to 1 the receiver will ignore collision activity When set to 0 defau...

Page 53: ...in the descriptor s cmdsts will be set A value of 0 is illegal and the results are undefined This value is also used to compare with the accumulated packet length for early receive indication When th...

Page 54: ...d can occur if the DP83816 has not completed a pending packet transmit or receive Situation 2 is a clock start event and can occur if the DP83816 has been programmed to a WOL state and it receives a w...

Page 55: ...tch is detected and the WKPAT0 bit is set RO cleared on read 26 ARPR ARP Received Set to 1 if an ARP packet has been detected and the WKARP bit is set RO cleared on read 25 BCASTR Broadcast Received S...

Page 56: ...for processing this is a feature of the DP83816 In addition to the above Wake on LAN features DP83816 also provides Wake on Pattern Matching Wake on DA match and Wake on Magic Packet Wake on Pattern...

Page 57: ...reception R W 29 PS_DA Pause on DA When set to 1 this bit enables reception of a pause frame based on a DA match with either the perfect match register or one of the pattern match buffers R W 28 24 un...

Page 58: ...the packet to be accepted 27 APM Accept on Perfect Match When set to 1 this bit allows the perfect match register to be used to compare against the DA for packet acceptance When this bit is 0 the perf...

Page 59: ...RFDR Perfect Match Register PMATCH 000h PMATCH octets 1 0 002h PMATCH octets 3 2 004h PMATCH octets 5 4 Pattern Count Registers PCOUNT 006h PCOUNT1 PCOUNT0 008h PCOUNT3 PCOUNT2 SecureOn Password Regis...

Page 60: ...ct match register octets 1 0 iow l RFDR 0008 write address octets 1 0 iow l RFCR 0002 perfect match register octets 3 2 iow l RFDR 0717 write address octets 3 2 iow l RFCR 0004 perfect match register...

Page 61: ...byte0 3FA Pattern2Word7E byte1 byte0 3F8 Pattern3Word1 byte1 byte0 306 Pattern2Word1 byte1 byte0 304 Pattern3Word0 byte1 byte0 302 Pattern2Word0 byte1 byte0 300 Pattern1Word3F byte1 byte0 2FE Pattern0...

Page 62: ...rn into buffer 1 iow l RFCR PATBUF01 2 iow l RFDR 1012 iow l RFCR PATBUF01 6 iow l RFDR 1113 iow l RFCR PATBUF01 a iow l RFDR 1214 write data pattern into buffer 2 iow l RFCR PATBUF23 iow l RFDR 2022...

Page 63: ...is accessed through the RFCR and the RFDR Refer to Figure 4 2 for a memory map Below is example code for setting clearing a bit in the hash table Figure 4 2 Hash Table Memory 40h bytes addressed on wo...

Page 64: ...increment with every 32 bit access to the BRDR register 30 16 unused 15 0 ADDR Boot ROM Address 16 bit address used to access the external Boot ROM Tag BRDR Size 32 bits Hard Reset undefined Offset 00...

Page 65: ...ck as 0 This bit is used for test purposes only and should be set to 0 for normal counter operation 2 ACLR Clear all counters When set to a 1 this bit forces all counters to be reset to 0 This bit is...

Page 66: ...which are automatically rejected from the FIFO due to both wire errors and FIFO overruns 0064h RXFCSErrors 8 4 Packets received with frame check sequence errors This counter is incremented for each pa...

Page 67: ...time before any valid data will appear at the MII receive outputs 13 Speed Selection Speed Select Default dependent on the setting of the ANEG_SEL bits in the CFG register When auto negotiation is di...

Page 68: ...needed only once after reset invalid opcode or invalid turnaround 0 Normal management operation 5 Auto Negotiation Complete Auto Negotiation Complete Default 0 1 Auto Negotiation process complete 0 Au...

Page 69: ...PHYIDR2 Size 16 bits Hard Reset 5C21h Offset 008Ch Access Read Only Bit Bit Name Description 15 10 OUI_LSB OUI Least Significant Bits Default 01 0111 Bits 19 to 24 of the OUI 080017h are mapped to bi...

Page 70: ...Selector Protocol Selection Bits Default 00001 These bits contain the binary encoded protocol selector supported by this port 00001 indicates that this device supports IEEE 802 3u Tag ANLPAR Size 16...

Page 71: ...etected via the Parallel Detection function 0 A fault has not been detected 3 LP_NP_ABLE Link Partner Next Page Able 1 Link Partner does support Next Page 0 Link Partner does not support Next Page 2 N...

Page 72: ...Reset 0000h Offset 00C0h Access Read Only Bit Bit Name Description 15 14 Reserved Reserved Write ignored read as 0 13 Receive Error Latch Receive Error Latch This bit will be cleared upon a read of t...

Page 73: ...operation 2 Duplex Status Duplex This bit indicates duplex status and is determined from Auto Negotiation or Forced Modes 1 Full duplex mode 0 Half duplex mode Note This bit is only valid if Auto Nego...

Page 74: ...the PHY to generate an interrupt at the end of each management read to facilitate interrupt testing 1 Generate an interrupt 0 Do not generate interrupt Tag MISR Size 16 bits Hard Reset 0000h Offset 0...

Page 75: ...s its max count FFh Tag RECR Size 16 bits Hard Reset 0000h Offset 00D4h Access Read Write Bit Bit Name Description 15 8 Reserved Reserved Writes ignored Read as 0 7 0 RXERCNT 7 0 RXER Counter Default...

Page 76: ...11 PSR_15 BIST Sequence select Selects length of LFSR used in BIST 1 PSR15 selected 0 PSR9 selected 10 BIST_STATUS BIST Test Status Default 0 LL RO 1 BIST pass 0 BIST fail Latched cleared by write to...

Page 77: ...arity 0 Normal polarity 4 POLARITY 10 Mb s Polarity Status RO LH This bit is a duplication of bit 12 in the PHYSTS register Both bits will be cleared upon a read of either register 1 Inverted Polarity...

Page 78: ...nts per descriptor DP83816 only supports a single fragment per descriptor By default DP83816 will use the descriptor format shown above By setting CFG EUPHCOMP software may force compatibility with th...

Page 79: ...l during the transmission of this packet was excessive 3 2 ms indicating transmission failure 21 OWC Out of Window Collision The MAC encountered an out of window collision during the transmission of t...

Page 80: ...d do not cause any bus activity nor do they consume receive descriptors However this condition could occur if the packet is rejected by the Receive Filter later in the packet than the receive drain th...

Page 81: ...1 4 Descriptor Lists Descriptors are organized in linked lists using the link field The system designer may also choose to implement a ring of descriptors by linking the last descriptor in the list ba...

Page 82: ...ck Waiting for free space in the TxDataFIFO to reach TxFillThreshold txFragRead Waiting for the transfer of a fragment or portion of a fragment from the PCI bus to the TxDataFIFO txDescWrite Waiting f...

Page 83: ...ngth will be the minimum of txFifoAvail and descCnt Decrement descCnt accordingly descCnt 0 MORE txDescWrite Start a burst transfer to write the status back to the descriptor clearing the OWN bit desc...

Page 84: ...nd the SIZE field from the cmdsts field of the current descriptor to keep the TxDataFifo full It also uses the MORE bit and the SIZE field from the cmdsts field of the current descriptor to know when...

Page 85: ...g for the transfer of a descriptor from the PCI bus into the RxDescCache rxFifoBlock Waiting for the amount of data in the RxDataFifo to reach the RxDrainThreshold or to represent a complete packet rx...

Page 86: ...Ptr The length will be the minimum of rxPktBytes and descCnt Decrement descCnt accordingly descCnt 0 rxPktBytes 0 rxDescWrite Start a burst transfer to write the status back to the descriptor setting...

Page 87: ...e device reads in the first descriptor into the RxDescCache 3 As data arrives in the RxDataFIFO the receive buffer management state machine places the data in the receive buffer described by the descr...

Page 88: ...ta se quence which can be located anywhere within the packet but must be preceded by a synchronization stream The packet must also meet the basic require ments for the LAN technology chosen e g ethern...

Page 89: ...n conjunction with the PCI Power Management states detailed in the previous section The DP83816 supports several wake events including but not limited to Wake on PHY Interrupt i e link change Wake on...

Page 90: ...t was a packet this will now be emptied from the receive FIFO via DMA 6 6 Sleep Mode Sleep Mode is a system level function that allows a device to be placed in a lower power mode than WOL mode In slee...

Page 91: ...se specified Note 1 These values ensure 3 3V and 5V compatibility Note 2 For IDD Measurements outputs are not loaded Symbol Parameter Conditions Min Typ Max Units VOH Minimum High Level Output Voltage...

Page 92: ...ng 7 2 2 X1 Clock Timing Number Parameter Min Max Units 7 2 1 1 PCICLK Low Time 12 ns 7 2 1 2 PCICLK High Time 12 ns 7 2 1 3 PCICLK Cycle Time 30 ns Number Parameter Min Max Units 7 2 2 1 X1 Low Time...

Page 93: ...iod will be ignored Note EE is disabled for non power on reset 7 2 4 Non Power On Reset Note Minimum reset complete time is a function of the PCI transmit and receive clock frequencies Number Paramete...

Page 94: ...DP83816 7 2 5 POR PCI Inactive Number Parameter Min Max Units 7 2 5 1 VDD stable to EE access VDD indicates the digital supply AUX power plane except PCI bus power Guaranteed by design 60 us 7 2 5 2 E...

Page 95: ...Min Max Units 7 2 6 1 Input Setup Time 7 ns 7 2 6 2 Input Hold Time 0 ns 7 2 6 3 Output Valid Delay 2 11 ns 7 2 6 4 Output Float Delay toff time 28 ns 7 2 6 5 Output Valid Delay for REQN point to poi...

Page 96: ...d PCICLK FRAMEN AD 31 0 C BEN 3 0 IRDYN TRDYN DEVSELN PAR PERRN Addr Data IDSEL Cmd BE T1 T1 T1 T1 T2 T2 T1 T2 T2 T2 T1 T2 T3 T4 T3 T4 T1 T2 T4 T2 T3 T1 T2 PCICLK FRAMEN AD 31 0 C BEN 3 0 IRDYN TRDYN...

Page 97: ...PCICLK FRAMEN AD 31 0 C BEN 3 0 IRDYN TRDYN DEVSELN PAR PERRN Addr Data Cmd BE T3 T3 T3 T3 T3 T4 T4 T3 T3 T3 T4 T1 T2 T1 T2 T3 T4 T1 T2 T4 T3 T4 PCICLK FRAMEN AD 31 0 C BEN 3 0 IRDYN TRDYN DEVSELN PA...

Page 98: ...t Read PCICLK FRAMEN AD 31 0 C BEN 3 0 IRDYN TRDYN DEVSELN PAR PERRN Addr Data Cmd BE T1 T1 T1 T2 T2 T1 T2 T2 T1 T2 T3 T4 T3 T4 T1 T2 T4 T2 T3 T1 PCICLK FRAMEN AD 31 0 C BEN 3 0 IRDYN TRDYN DEVSELN PA...

Page 99: ...ational com DP83816 PCI Bus Master Burst Write PCI Bus Arbitration PCICLK FRAMEN AD 31 0 C BEN 3 0 IRDYN TRDYN DEVSELN PAR PERRN Addr Data Cmd BE T3 T3 T3 T3 T3 T4 T4 T3 T3 T3 T4 T1 T2 T1 T2 T3 T4 T1...

Page 100: ...Min Max Units 7 2 7 1 EECLK Cycle Time 4 us 7 2 7 2 EECLK Delay from EESEL Valid 1 us 7 2 7 3 EECLK Low to EESEL Invalid 2 us 7 2 7 4 EECLK to EEDO Valid 2 us 7 2 7 5 EEDI Setup Time to EECLK 2 us 7 2...

Page 101: ...lse Width 180 ns 7 2 8 6 Data Hold Time from MRDN Invalid 0 ns 7 2 8 7 Data Invalid from MWRN Invalid 60 ns 7 2 8 8 Data Valid to MWRN Valid 30 ns 7 2 8 9 Address Setup Time to MWRN Valid 30 ns 7 2 8...

Page 102: ...e On Delay is determined by measuring the time from the first bit of the J code group to the assertion of Carrier Sense Note 1 bit time 10 ns in 100 Mb s mode Note The Ideal window recognition region...

Page 103: ...Notes Min Typ Max Units 7 2 10 1 End of Packet High Time with 0 ending bit 10 Mb s 300 ns 7 2 10 2 End of Packet High Time with 1 ending bit 10 Mb s 250 ns Parameter Description Notes Min Typ Max Unit...

Page 104: ...eceive timings Parameter Description Notes Min Typ Max Units 7 2 12 1 Pulse Width 100 ns 7 2 12 2 Pulse Period 16 ms Parameter Description Notes Min Typ Max Units 7 2 13 1 Clock Data Pulse Width 100 n...

Page 105: ...MDIO to MDC Setup 10 10 ns 7 2 14 3 MDIO from MDC Hold 10 ns 7 2 14 4 RXD to RXCLK Setup 10 ns 7 2 14 5 RXD from RXCLK Hold 10 ns 7 2 14 6 RXDV RXER to RXCLK Setup 10 ns 7 2 14 7 RXDV RXER from RXCLK...

Page 106: ...105 www national com DP83816 Notes...

Page 107: ...l component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to af fect its safety o...

Page 108: ...or use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have...

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