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Introduction to the ARM

®

Processor

Using Intel FPGA Toolchain

For Quartus Prime 16.1

1

Introduction

This tutorial presents an introduction to the ARM

®

Cortex-A9 processor, which is a processor implemented as a

hardware block in Intel’s Cyclone

®

V SoC FPGA devices. The tutorial is intended for a user who wishes to use an

ARM-based system on Intel’s DE1-SOC board.

A full description of ARM processors is provided in the

ARM Architecture Reference Manual

, which is available on

the ARM Holdings web site.

Contents

:

• Overview of ARM Cortex-A9 Processor Features

• Register Structure

• Instruction Sets

• Accessing Memory and I/O Devices

• Addressing Modes

• ARM Instructions

• Assembler Directives

• Example Program

• Operating Modes

• Banked Registers

• Exception Processing

• Input/Output Operations

Intel Corporation - FPGA University Program

November 2016

1

Summary of Contents for ARM Cortex-A9

Page 1: ...an ARM based system on Intel s DE1 SOC board A full description of ARM processors is provided in the ARM Architecture Reference Manual which is available on the ARM Holdings web site Contents Overvie...

Page 2: ...ral purpose registers R0 to R14 a Program Counter R15 and a Current Program Status Register CPSR as shown in Figure 1 All general purpose registers can be used in the same way However software program...

Page 3: ...s called banked registers for saving the contents of primary registers when various types of interrupts occur as discussed in Section 10 4 Instruction Sets The ARM Cortex A9 processor can execute inst...

Page 4: ...base register and a value that is either given as a signed 12 bit offset directly in the instruction or as a magnitude in the index register The magnitude in Rm can be scaled by shifting it either lef...

Page 5: ...hift Address Rn Rn Rn Rm shifted offset a signed number given in the instruction shift direction integer where direction is LSL for left shift or LSR for right shift and integer is a 5 bit unsigned nu...

Page 6: ...will determine the immediate offset as the difference between the address MEMLOC and the contents of the updated Program Counter It will generate the instruction LDR R2 R15 offset This offset takes in...

Page 7: ...emory and I 0 interfaces and the general purpose registers The LDR Load Register instruction illustrated in the previous section loads a 32 bit operand into a register The corresponding Store instruct...

Page 8: ...o not have to be contiguous A range of registers is specified by listing the first and the last registers in the range separated by a dash In the resulting machine instruction each register is identif...

Page 9: ...B SP R1 R3 R5 The instruction POP R1 R3 R5 restores the contents of these registers from the stack The equivalent Load Multiple instruction would be LDMIA SP R1 R3 R5 6 2 Data Processing Instructions...

Page 10: ...its value can be shifted before being used If it is shifted then the shifting amount can be specified as a five bit constant as in OP Rd Rn Rm LSL 3 or as the least significant byte of a register Rs...

Page 11: ...in ADD R0 R1 24 The Assembler will implement this operation with the Subtract instruction SUB R0 R1 24 6 4 1 Multiplication There are two versions of multiplication instructions MUL Multiply MLA Mult...

Page 12: ...uctions that perform logic operations for testing purposes The Test instruction TST Rn Operand2 performs the AND operation using the contents of Rn and Operand2 and sets the condition code flags based...

Page 13: ...sing mode to access the literal pool The Assembler decides where in memory to place the literal pool typically it is immediately following the program s machine code A constant may be represented by a...

Page 14: ...wo registers or the contents of a register and an immediate value and set the condition code flags based on the result The Compare instruction CMP Rn Operand2 performs the comparison by subtracting th...

Page 15: ...f data processing instructions is OP S cond Rd Rn Operand2 The conditions that can be specified are those in Table 2 Observe that there are 14 patterns for conditions that depend on the condition code...

Page 16: ...d operation of the ARM processor The branch instruction is executed conditionally based on the current setting of the Condition Code flags The conditions that can be specified are given in Table 2 For...

Page 17: ...that if nested subroutines are used it is necessary to save the contents of R14 typically on the stack prior to a nested subroutine call We should also mention that in the ARM environment there is a c...

Page 18: ...ymbol visible outside the assembled object file hword expressions Expressions separated by commas are specified Each expression is assembled into a 16 bit number include filename Provides a mechanism...

Page 19: ...st instruction in the program The execution of the program ends by continuously looping on this instruction text global _start _start LDR R0 AVECTOR Register R0 is a pointer to vector A LDR R1 BVECTOR...

Page 20: ...d by a program executing a Supervisor Call instruction SVC It is also entered on reset or power up Abort mode is entered if a program attempts to access a non existing memory location Undefined mode i...

Page 21: ...re efficient some other registers are involved These registers are shown in blue in Figure 4 They are called the banked registers There is a different set of banked registers for each exception mode A...

Page 22: ...service routine needs to use some of these registers the contents of the registers must be saved on the stack and later restored However having the five banked registers R8_fiq to R12_fiq in the FIQ m...

Page 23: ...anked saved status register that is accessed Thus MRS Rd SPSR copies the contents of SPSR_irq into register Rd 11 Exception Processing An exception in the normal flow of program execution can be cause...

Page 24: ...A software interrupt which is called a software exception in ARM literature occurs when an SVC instruction is encountered in a program This instruction causes the processor to switch into Supervisor m...

Page 25: ...e processor saves the contents of CPSR in the SPSR_irq register and it saves the contents of PC in the link register LR_irq It also sets the mode bits in CPSR to denote the IRQ exception mode and it s...

Page 26: ...d with the instruction SUBS PC LR 8 11 6 Nested Interrupts When two or more interrupts or exceptions occur at different priority levels causing the processor to enter different modes of operation thei...

Page 27: ...gure 5 illustrates the structure of the code that can be used text global _start LDR PC _start Go to the beginning of the MAIN program LDR PC SERVICE_UND Unimplemented instruction LDR PC SERVICE_SVC S...

Page 28: ...al to ensure that the cached data is not used instead of the current values in the I O device registers In effect the data cache has to be bypassed when reading or writing the registers in I O devices...

Page 29: ...ifications in accordance with Intel s stan dard warranty but reserves the right to make changes to any products and services at any time without notice Intel assumes no responsibility or liability ari...

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