Fujitsu MPC3045AH Product Manual Download

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C141-E056-02EN

MPC3045AH
MPC3065AH

DISK DRIVES

PRODUCT MANUAL

Summary of Contents for MPC3045AH

Page 1: ...C141 E056 02EN MPC3045AH MPC3065AH DISK DRIVES PRODUCT MANUAL ...

Page 2: ...s 01 May 1998 02 Dec 1998 Pages 1 4 4 14 5 9 5 16 5 30 5 35 5 37 5 52 to 5 54 5 63 5 64 5 69 5 81 6 8 6 9 to 6 23 revised Specification No C141 E056 EN The contents of this manual is subject to change without prior notice All Rights Reserved Copyright 1998 FUJITSU LIMITED ...

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Page 4: ...isk drives into user systems This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems This manual consists of the following six chapters Chapter 1 DEVICE OVERVIEW Chapter 2 DEVICE CONFIGURATION Chapter 3 INSTALLATION CONDITIONS Chapter 4 THEORY OF DEVICE OPERATION Chapter 5 INTERFACE Chapter 6 OPERATIONS In this manual disk drives may be r...

Page 5: ...situation could result in minor or moderate personal injury if the user does not perform the procedure correctly This alert signal also indicates that damages to the product or other property may occur if the user does not perform the procedure correctly This indicates information that could help the user use the product more efficiently In the text the alert signal is centered followed below by t...

Page 6: ...e adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk drive ...

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Page 8: ... Noise 1 8 1 6 Shock and Vibration 1 9 1 7 Reliability 1 9 1 8 Error Rate 1 10 1 9 Media Defects 1 10 CHAPTER 2 DEVICE CONFIGURATION 2 1 2 1 Device Configuration 2 1 2 2 System Configuration 2 3 2 2 1 ATA interface 2 3 2 2 2 1 drive connection 2 3 2 2 3 2 drives connection 2 4 CHAPTER 3 INSTALLATION CONDITIONS 3 1 3 1 Dimensions 3 1 3 2 Mounting 3 3 3 3 Cable Connections 3 7 3 3 1 Device connector...

Page 9: ...2 Execution timing of self calibration 4 8 4 5 3 Command processing during self calibration 4 8 4 6 Read write Circuit 4 9 4 6 1 Read write preamplifier PreAMP 4 9 4 6 2 Write circuit 4 9 4 6 3 Read circuit 4 11 4 6 4 Time base generator circuit 4 13 4 7 Servo Control 4 14 4 7 1 Servo control circuit 4 15 4 7 2 Data surface servo format 4 18 4 7 3 Servo frame format 4 18 4 7 4 Actuator motor contr...

Page 10: ... 5 5 3 2 The data in transfer 5 73 5 5 3 3 Pausing an Ultra DMA data in burst 5 73 5 5 3 4 Terminating an Ultra DMA data in burst 5 74 5 5 4 Ultra DMA data out commands 5 76 5 5 4 1 Initiating an Ultra DMA data out burst 5 76 5 5 4 2 The data out transfer 5 77 5 5 4 3 Pausing an Ultra DMA data out burst 5 77 5 5 4 4 Terminating an Ultra DMA data out burst 5 78 5 5 5 Ultra DMA CRC rules 5 80 5 5 6 ...

Page 11: ...6 OPERATIONS 6 1 6 1 Device Response to the Reset 6 1 6 1 1 Response to power on 6 2 6 1 2 Response to hardware reset 6 3 6 1 3 Response to software reset 6 4 6 1 4 Response to diagnostic command 6 5 6 2 Address Translation 6 6 6 2 1 Default parameters 6 6 6 2 2 Logical address 6 7 6 3 Power Save 6 8 6 3 1 Power save mode 6 8 6 3 2 Power commands 6 10 6 4 Defect Management 6 10 6 4 1 Spare area 6 ...

Page 12: ... Jumper location 3 9 3 11 Factory default setting 3 10 3 12 Jumper setting of master or slave device 3 10 3 13 Jumper setting of Cable Select 3 11 3 14 Example 1 of Cable Select 3 11 3 15 Example 2 of Cable Select 3 11 4 1 Head structure 4 2 4 2 MPC30xxAH Block diagram 4 4 4 3 Power on operation sequence 4 6 4 4 Read write circuit block diagram 4 10 4 5 Frequency characteristic of programmable fil...

Page 13: ...t terminating an Ultra DMA data in burst 5 90 5 15 Initiating an Ultra DMA data out burst 5 91 5 16 Sustained Ultra DMA data out burst 5 92 5 17 Device pausing an Ultra DMA data out burst 5 93 5 18 Host terminating an Ultra DMA data out burst 5 94 5 19 Device terminating an Ultra DMA data out burst 5 95 5 20 Power on Reset Timing 5 96 6 1 Response to power on 6 2 6 2 Response to hardware reset 6 3...

Page 14: ... interface connector 5 3 5 3 I O registers 5 7 5 4 Command code and parameters 5 14 5 5 Information to be read by IDENTIFY DEVICE command 5 30 5 6 Features register values and settable modes 5 34 5 7 Diagnostic code 5 37 5 8 Features Register values subcommands and functions 5 48 5 9 Format of device attribute value data 5 50 5 10 Format of insurance failure threshold value data 5 51 5 11 Contents...

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Page 16: ...A controller The disk drive is compact and reliable 1 1 Features 1 1 1 Functions and performance 1 Compact The disk has 1 2 or 3 disks of 95 mm 3 5 inches diameter and its height is 25 4 mm 1 inch 2 Large capacity The disk drive can record up to 2 170 MB formatted on one disk using the 8 9 PRML recording method and 15 recording zone technology The MPC3045AH and MPC3065AH have a formatted capacity ...

Page 17: ...isk drive can be connected to an ATA interface of a personal computer 2 256 KB data buffer The disk drive uses a 512 KB data buffer to transfer data between the host and the disk media In combination with the read ahead cache system described in item 3 and the write cache described in item 6 the buffer contributes to efficient I O processing 3 Read ahead cache system After the execution of a disk ...

Page 18: ...ery The 24 byte ECC has improved buffer error correction for correctable data errors 6 Write cache When the disk drive receives a write command the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media This feature reduces the access time at writing ...

Page 19: ... ms typical Start Stop time Start 0 rpm to Drive Read Stop at Power Down Typical 8 sec Maximum 16 sec Typical 20 sec Maximum 30 sec Interface ATA 3 Maximum Cable length 0 46 m Data Transfer Rate To From Media 12 65 to 19 18 MB s To From Host 16 7 MB s Max burst PIO mode 4 burst DMA mode 2 33 3 MB s Max burst ultra DMA mode 2 Data buffer 512 KB Physical Dimensions Height Width Depth 26 1 mm max 101...

Page 20: ...ames and product numbers Model Name Capacity user area Mounting Screw Order No Others MPC3045AH 4551 96 No 6 32UNC CA01742 B641 MPC3065AH 6510 55 No 6 32UNC CA01742 B661 1 3 Power Requirements 1 Input Voltage 5 V 5 12 V 8 2 Ripple 12 V 5 V Maximum 200 mV peak to peak 100 mV peak to peak Frequency DC to 1 MHz DC to 1 MHz ...

Page 21: ... 8 Sleep 4 150 0 8 1 Current is typical rms except for spin up 2 Power requirements reflect nominal values for 12V and 5V power 3 Idle mode is in effect when the drive is not reading writing seeking or executing any commands A portion of the R W circuitry is powered down the spindle motor is up to speed and the Drive ready condition exists 4 R W mode is defined as 50 read operations and 50 write o...

Page 22: ... seconds Figure 1 1 Current fluctuation Typ when power is turned on 5 Power on off sequence The voltage detector circuit monitors 5 V and 12 V The circuit does not allow a write signal if either voltage is abnormal This prevents data from being destroyed and eliminates the need to be concerned with the power on off sequence ...

Page 23: ...ximum Wet Bulb 8 to 80 RH Non condensing 5 to 85 RH Non condensing 29 C Altitude relative to sea level Operating Non operating 60 to 3 000 m 200 to 10 000 ft 60 to 12 000 m 200 to 40 000 ft 1 5 Acoustic Noise Table 1 5 lists the acoustic noise specification Table 1 5 Acoustic noise specification Model MPC3045AH MPC3065AH Idle mode DRIVE READY 3 9 bels Seek mode Random 4 4 bels Sound Pressure Typic...

Page 24: ...ts refers to defects that involve repair readjustment or replacement Disk drive defects do not include failures caused by external factors such as damage caused by handling inappropriate operating environments defects in the power supply host system or interface cable 2 Mean time to repair MTTR The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member ...

Page 25: ...annot be recovered by maximum 126 times read retries without user s retry and ECC corrections shall occur no more than 10 times when reading data of 1015 bits Read retries are executed according to the disk drive s error recovery procedure and include read retries accompanying head offset operations 2 Positioning error Positioning seek errors that can be recovered by one retry shall occur no more ...

Page 26: ...iguration 2 1 Device Configuration Figure 2 1 shows the disk drive The disk drive consists of a disk enclosure DE read write preamplifier and controller PCA The disk enclosure contains the disk media heads spindle motors actuators and a circulating air filter Figure 2 1 Disk drive outerview ...

Page 27: ...ry for controlling positioning and read write and user data are written Numerals 0 to 5 indicate read write heads MPC3065AH Model MPC3045AH Model Spindle 0 1 3 2 Actuator Spindle 1 2 0 3 5 4 Actuator Figure 2 2 Configuration of disk media heads 3 Spindle motor The disks are rotated by a direct drive Hall less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which co...

Page 28: ...ity by preventing errors caused by external noise 7 Controller circuit The controller circuit consists of an LSI chip to improve reliability The high speed microprocessor unit MPU achieves a high performance AT controller 2 2 System Configuration 2 2 1 ATA interface Figures 2 3 and 2 4 show the ATA interface system configuration The drive has a 40 pin PC AT interface connector and supports the PIO...

Page 29: ... and receiver ATA is an abbreviation of AT attachment The disk drive is conformed to the ATA 3 interface At high speed data transfer PIO mode 3 mode 4 DMA mode 2 or ultra DMA mode 2 occurrence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal line...

Page 30: ...INSTALLATION CONDITIONS 3 1 Dimensions 3 2 Mounting 3 3 Cable Connections 3 4 Jumper Settings 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm ...

Page 31: ...C141 E056 01EN 3 2 Figure 3 1 Dimensions ...

Page 32: ...closure DE body is connected to signal ground SG and the mounting frame is also connected to signal ground These are electrically shorted Note Use No 6 32UNC screw for the mounting screw and the screw length should satisfy the specification in Figure 3 4 3 Limitation of side mounting When the disk drive is mounted using the screw holes on both side of the disk drive use two screw holes shown in Fi...

Page 33: ...e 3 4 Mounting frame structure 5 0 or less 4 5 or less 2 B Frame of system cabinet Details of B Details of A Frame of system cabinet Screw Screw PCA DE 2 5 2 5 2 5 A DE Side surface mounting Bottom surface mounting Do not use this screw holes Use these screw holes ...

Page 34: ... in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure 3 5 Surface temperature measurement points Table 3 1 Surface temperature measur...

Page 35: ...on Figure 3 6 Service area 6 External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields P side Cable connection Mode setting switches R side Mounting screw hole Mounting screw hole Q side Mounting screw hole ...

Page 36: ...connectors and terminals listed below for connecting external devices Figure 3 7 shows the locations of these connectors and terminals Power supply connector CN1 ATA interface connector CN1 Figure 3 7 Connector locations ATA interface connector Mode Setting Pins Power supply connector CN1 ...

Page 37: ...424 0 AMP Contact 60617 4 AMP Signal cable AWG 18 to 24 Note The cable of twisted pairs and neighboring line separated individually is not allowed to use for the host interface cable It is because that the location of signal lines in these cables is not fixed and so the problem on the crosstalk among signal lines may occur 3 3 3 Device connection Figure 3 8 shows how to connect the devices ATA int...

Page 38: ... 12VDC 4 3 2 1 Figure 3 9 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 10 shows the location of the jumpers to select drive configuration and functions A39 A40 Interface Connector Mode setting Connector pins Power supply connector C01 C04 B01 02 B06 B05 B05 06 A01 02 A39 40 CN1 A01 A02 B02 C04 C01 B01 Figure 3 10 Jumper location ...

Page 39: ...ult setting 3 4 3 Jumper configuration 1 Device type Master device device 0 or slave device device 1 is selected 06 B02 05 B01 a Master device b Slave device B01 05 06 B02 Figure 3 12 Jumper setting of master or slave device 2 Cable Select CSEL In Cable Select mode the device can be configured either master device or slave device For use of Cable Select function Unique interface cable is needed ...

Page 40: ...the cable and connecting it to ground further the CSEL is set to low level The device is identified as a master device At this time the CSEL of the slave device does not have a conductor Thus since the slave device is not connected to the CSEL conductor the CSEL is set to high level The device is identified as a slave device Open CSEL conductor GND Slave device Master device Host system Figure 3 1...

Page 41: ... 3 5 2 4 6 Slave Device Master Device 1 3 5 2 4 6 1 3 5 Cable Select Model No of cylinders No of heads No of sectors MPC3045AH 9 408 15 63 MPC3065AH 13 456 15 63 b Special mode 2 4 6 1 3 5 2 4 6 Slave Device Master Device 1 3 5 2 4 6 1 3 5 Cable Select Model No of cylinders No of heads No of sectors MPC3045AH 4 092 16 63 MPC3065AH 4 092 16 63 ...

Page 42: ...isk drive and drive control method 4 2 Subassemblies The disk drive consists of a disk enclosure DE and printed circuit assembly PCA The DE contains all movable parts in the disk drive including the disk spindle actuator read write head and air filter For details see Subsections 4 2 1 to 4 2 5 The PCA contains the control circuits for the disk drive The disk drive has one PCA For details see Secti...

Page 43: ...ervo information 4 2 4 Actuator The actuator consists of a voice coil motor VCM and a head carriage The VCM moves the head carriage along the inner or outer edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head 4 2 5 Air filter There are two types of air ...

Page 44: ... the 8 9 group coded recording GCR encoder and decoder and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice coi...

Page 45: ...C141 E056 01EN 4 4 Figure 4 2 MPC30xxAH Block diagram ...

Page 46: ... read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM This unlocks the heads which are parked at the inner circumference of the disks d The disk drive positions the heads onto the SA area and reads out the system information e ...

Page 47: ...uffer write read test The spindle motor starts Self diagnosis 1 MPU bus test Inner register write read test Work RAM write read test Start Power on Drive ready state command waiting state Execute self calibration Initial on track and read out of system information f e d End Figure 4 3 Power on operation sequence ...

Page 48: ...ation The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value of the VCM has a dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque constant value c...

Page 49: ...About 30 minutes 3 About 30 minutes About 60 minutes 4 About 30 minutes About 90 minutes 5 About 30 minutes About 120 minutes 6 About 30 minutes About 150 minutes 7 9 Every about 30 minutes 4 5 3 Command processing during self calibration If the disk drive receives a command execution request from the host while executing self calibration according to the timechart the disk drive terminates self c...

Page 50: ...e circuit The write data is output from the hard disk controller HDC with the NRZ data format and sent to the encoder circuit in the RDC with synchronizing with the write clock The NRZ write data is converted from 8 bit data to 9 bit data by the encoder circuit then sent to the PreAMP and the data is written onto the media 1 8 9 GCR The disk drive converts data using the 8 9 0 4 4 group coded reco...

Page 51: ...C141 E056 01EN 4 10 Figure 4 4 Read write circuit block diagram ...

Page 52: ...s due to the head characteristics or outer inner head positions 2 Programmable filter The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off frequency of the low pass filter and boost up gain are controlled from each DAC circuit in read ch...

Page 53: ...C141 E056 01EN 4 12 Figure 4 6 PR4 signal transfer ...

Page 54: ...rom a synthesizer 6 8 9 GCR decoder This circuit converts the 9 bit read data into the 8 bit NRZ data 4 6 4 Time base generator circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radiu...

Page 55: ...6 to 9590 9591 to 10423 Transfer rate MB s 16 86 16 51 15 73 14 96 14 33 13 70 12 65 The MPU transfers the data transfer rate setup data SDATA SCLK to the RDC that includes the time base generator circuit to change the data transfer rate 4 7 Servo Control The actuator motor and the spindle motor are submitted to servo control The actuator motor is controlled for moving and positioning the head to ...

Page 56: ...rvo control circuit 1 Microprocessor unit MPU The MPU includes DSP unit etc and the MPU starts the spindle motor moves the heads to the reference cylinders seeks the specified cylinder and executes calibration according to the internal operations of the MPU The major internal operations are listed below a Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is...

Page 57: ... the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration value Figure 4 8 Physical sector servo configuration on disk surface Servo frame 54 servo frames revolution ...

Page 58: ...mplifier feeds currents corresponding to the DAC output signal voltage to the VCM 6 Spindle motor control circuit The spindle motor control circuit controls the sensor less spindle motor This circuit detects number of revolution of the motor by the interrupt generated periodically compares with the target revolution speed then flows the current into the motor coil according to the differentiation ...

Page 59: ...er position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving 4 7 3 Servo frame format As the servo information the drive uses the two phase servo generated from the gray code and servo A to D This servo information is used for positioning operation of radius direction and position detection of circumstance direction The servo fra...

Page 60: ... fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the target t...

Page 61: ...ompensation These are digitally controlled by the firmware 4 7 5 Spindle motor control Hall less three phase eight pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC hereafter The firmware operates on the MPU manufactured by Fujitsu The spindle motor is controlled by sending several signals from the ...

Page 62: ...e stable rotation mode 3 Stable rotation mode The MPU calculates a time for one revolution of the spindle motor based on the PHASE signal from the SVC The MPU takes a difference between the current time and a time for one revolution at 7 200 rpm that the MPU already recognized Then the MPU keeps the rotational speed to 7 200 rpm by charging or discharging the charge pump for the different time For...

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Page 64: ...C141 E056 01EN 5 1 CHAPTER 5 INTERFACE 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA feature set 5 6 Timing ...

Page 65: ...us bit 11 DD11 Data bus bit 12 DD12 Data bus bit 13 DD13 Data bus bit 14 DD14 Data bus bit 15 DD15 Device active or slave present see note DASP Device address bit 0 DA0 Device address bit 1 DA1 Device address bit 2 DA2 DMA acknowledge DMACK DMA request DMARQ Interrupt request INTRQ I O read DIOR DMA ready during Ultra DMA data in bursts HDMARDY Data strobe during Ultra DMA data out bursts HSTROBE ...

Page 66: ...12 DATA13 DATA14 DATA15 KEY GND GND GND CSEL GND reserved PDIAG DA2 CS1 GND signal I O Description RESET I Reset signal from the host This signal is low active and is asserted for a minimum of 25 µs during power on DATA 0 15 I O Sixteen bit bi directional data bus between the host and the device These signals are used for data transfer DIOW STOP I DIOW is the strobe signal asserted by the host to ...

Page 67: ...register by the host Completion of sector data transfer without reading the Status register When the device is not selected or interrupt is disabled the INTRQ Signal shall be in a high impedance state CS0 I Chip select signal decoded from the host address bus This signal is used by the host to select the command block registers CS1 I Chip select signal decoded from the host address bus This signal...

Page 68: ...vice When CSEL signal is open the IDD is a slave device This signal is pulled up with 240 kΩ resistor DMACK I The host system asserts this signal as a response that the host system receive data or to indicate that data is valid DMARQ O This signal is used for DMA transfer between the host system and the device The device asserts this signal when the device completes the preparation of DMA data tra...

Page 69: ...tor Number registers are LBA bits The sector No under the LBA mode proceeds in the ascending order with the start point of LBA0 defined as follows LBA0 Cylinder 0 Head 0 Sector 1 Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command the sector LBA address is not changed LBA Cylinder No Number of head Head No Number of sector track Sector No 1 5 2...

Page 70: ...nd X 1F7 1 1 X X X Invalid Invalid Control block registers 0 1 1 1 0 Alternate Status Device Control X 3F6 0 1 1 1 1 X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus DATA0 to DATA7 3 When reading the Drive Address register bit 7 i...

Page 71: ... IDNF X ABRT TK0NF AMNF X Unused Bit 7 Interface CRC error ICRC This bit indicates that an interface CRC error has occurred during an Ultra DMA data transfer The content of this bit is not applicable for Multiword DMA transfers Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error...

Page 72: ... in a read or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed successfully If the command is not completed successfully this register indicates the number of sectors to be transferred to complete the request...

Page 73: ...h order 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 8 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit...

Page 74: ... ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is set for no longer than 15 seconds after the IDD accepts reset b Within 400 ns from the host system starts writing to the Command register c Within 5 µs following transfer of 512 bytes data during execution of the READ SECTOR S WRITE S...

Page 75: ...us command was being executed The Error register indicates the additional information of the cause for the error 10 Command register X 1F7 The Command register contains a command code being sent to the device After this register is written the command execution starts immediately Table 5 3 lists the executable commands and their command codes This table also lists the necessary parameters for each...

Page 76: ...sets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state 5 3 Host Comma...

Page 77: ...Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y INITIALIZE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 1 N Y N N Y IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D EXECUTE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 0 N N N N D FORMAT TRA...

Page 78: ... 1 0 1 0 0 N N N N D SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 1 N N N N D Notes FR Features Register CY Cylinder Registers SC Sector Count Register DH Drive Head Register SN Sector Number Register R Retry at error 1 Without retry 0 with retry Y Necessary to set parameters Y Necessary to set parameters under the LBA...

Page 79: ... 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR xx At command completion I O registers contents to be read Bit 7 6 5 4 3 2 1 0 1F7H ST Status information 1F6H DH L DV End Head No LBA MSB 1F5H CH End cylinder address MSB LBA 1F4H CL End cylinder address LSB LBA 1F3H SN End sector No LBA LSB 1F2H SC X 00 1F1H ER Error information CM Command register FR Features register DH Dev...

Page 80: ... is not on the track specified by the host the device performs a implied seek After the head reaches to the specified track the device reads the target sector The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition Upon the completion of the command execution command block registers contain the cylinder head and sector addresses in the CHS mode ...

Page 81: ...ULTIPLE MODE command should be executed prior to the READ MULTIPLE command When the READ MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the v...

Page 82: ...xecution example of READ MULTIPLE command At command issuance I O registers setting contents 1F7H CM 1 1 0 0 0 1 0 0 1F6H DH L DV Start head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV End head No...

Page 83: ...rror information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like in the CHS mode are set The host system can select the DMA transfer mode by using th...

Page 84: ... BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain the cylinder head and sector number of the last sector verified If an error occurs the verify operation is terminated at the sector where the error occurred The command block registers contain the cylinder the head and the sector addresses in the CHS mode or t...

Page 85: ...by the host the device performs a implied seek After the head reaches to the specified track the device writes the target sector The data stored in the buffer and CRC code and ECC bytes are written to the data field of the corresponding sector s Upon the completion of the command execution the command block registers contain the cylinder head and sector addresses of the last sector written If an e...

Page 86: ... MODE command should be executed prior to the WRITE MULTIPLE command When the WRITE MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the value ...

Page 87: ... Error information Note When the command terminates due to error only the DV bit and the error information field are valid 7 WRITE DMA X CA or X CB This command operates similarly to the WRITE SECTOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a statu...

Page 88: ... 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8 WRITE VERIFY X 3C This command operates similarly to the WRITE SECTOR S command except that the device verifies each sector immediately...

Page 89: ...0 to X F This command performs the calibration Upon receipt of this command the device sets BSY bit of the Status register and performs a calibration When the device completes the calibration the device updates the Status register clears the BSY bit and generates an interrupt This command can be issued in the LBA mode At command issuance I O registers setting contents 1F7H CM 0 0 0 1 x x x x 1F6H ...

Page 90: ...e this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address At command issuance I O registers setting contents 1F7H CM 0 1 1 1 x x x x 1F6H DH L DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB xx xx At command completion I O registers contents to be ...

Page 91: ...thin a default area It is recommended that the host system refers the addressable user sectors total number of sectors in word 60 to 61 of the parameter information by the IDENTIFY DEVICE command At command issuance I O registers setting contents 1F7H CM 1 0 0 1 0 0 0 1 1F6H DH DV Max head No 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx Number of sectors track xx At command completion I O regi...

Page 92: ...ntents 1F7H CM 1 1 1 0 1 1 0 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information ...

Page 93: ...ber of current Cylinders 55 Variable Number of current Head 56 Variable Number of current sectors per track 57 58 Variable Total number of current sectors 59 8 Transfer sector count currently set by READ WRITE MULTIPLE command 60 61 X 0087A8C0 X 00C20790 Total number of user addressable sectors LBA mode only MPC3045AH X 0087A8C0 MPC3065AH X 00C20790 62 X 0000 Retired 63 X xx07 Multiword DMA transf...

Page 94: ...d Bit 11 IORDY support 1 Supported Bit 10 IORDY inhibition 0 Disable inhibition Bit 9 LBA support 1 Supported Bit 8 DMA support 1 Supported Bit 7 0 Vendor specific 6 Word 51 PIO data transfer mode Bit 15 8 PIO data transfer mode X 02 PIO mode 2 Bit 7 0 Vendor specific 7 Word 53 Enable disable setting of word 54 58 64 70 and 88 Bit 15 3 Reserved Bit 2 Enable disable setting of word 88 1 Enable Bit ...

Page 95: ...12 Write Buffer command supported 1 Bit 11 Write Buffer command supported Old Spec 1 Bit 10 Host Protected Area feature command supported 0 Bit 9 Device Reset command supported 0 Bit 8 SERVICE Interrupt supported 0 Bit 7 Release Interrupt supported 0 Bit 6 Lock Ahead supported 1 Bit 5 Write cache supported 1 Bit 4 Packet command feature set supported 0 Bit 3 Power Management feature set supported ...

Page 96: ...formation 14 SET FEATURES X EF The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed For the transfer mode Feature register 03 detail setting can be done using the Sector Count register Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Fe...

Page 97: ...d WRITE LONG commands X CC Enables the reverting to power on default settings after software reset At power on or after hardware reset the default mode is the same as that is set with a value greater than X AA except for write cache If X 66 is specified it allows the setting value greater than X AA which may have been modified to a new value since power on to remain the same even after software re...

Page 98: ... 00000 001 X 01 transfer mode not changed 15 SET MULTIPLE MODE X C6 This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands The block count number of sectors in a block for these commands are also specified by the SET MULTIPLE MODE command The number of sectors per block is written into the Sector Count register The IDD supports 2 4 8 and 16 sectors as the block co...

Page 99: ...or to software reset is retained after software reset The parameters for the multiple commands which are posted to the host system when the IDENTIFY DEVICE command is issued are listed below See Subsection 5 3 2 for the IDENTIFY DEVICE command Word 47 8010 Word 59 0000 01xx Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands are 16 fixed...

Page 100: ...The device 1 does not generate an interrupt A diagnostic status of the device 0 is read by the host system When a diagnostic failure of the device 1 is detected the host system can read a status of the device 1 by setting the DV bit selecting the device 1 When device 1 is not present The device 0 posts only the results of its own self diagnosis The device 0 clears the BSY bit of the Status registe...

Page 101: ... clears the DRQ bits sets the BSY bit However the device does not perform format operation but the drive clears the BYS bit and generates an interrupt soon When the command execution completes the device clears the BSY bit and generates an interrupt The drive supports this command for keep the compatibility with previous drive only 18 READ LONG X 22 or X 23 This command operates similarly to the R...

Page 102: ...mation 1 If the command is terminated due to an error this register indicates 01 19 WRITE LONG X 32 or X 33 This command operates similarly to the READ SECTOR S command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium The device does not generate ECC bytes by itself The WRITE LONG command supports only single sector operation This command...

Page 103: ...LBA LSB 00 1 Error information 1 If the command is terminated due to an error this register indicates 01 20 READ BUFFER X E4 The host system can read the current contents of the sector buffer of the device by issuing this command Upon receipt of this command the device sets the BSY bit of Status register and sets up the sector buffer for a read operation Then the device sets the DRQ bit of Status ...

Page 104: ...it of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the sector buffer then generates an interrupt At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 0 0 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2...

Page 105: ...wn function means that the device automatically enters the standby mode after a certain period of time When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer r...

Page 106: ... the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the automatic power down function At command issuance I O registers setting contents 1F7H CM X 95 or X E1 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H...

Page 107: ... the Sector Count register is 0 the automatic power down function is disabled Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as the READ SECTOR s command is received the device processes the command after driving the spindle motor At command issuance I O registers setting contents 1F7H CM X 96 or X E2 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F...

Page 108: ...ceipt of this command the device sets the BSY bit of the Status register and enters the sleep mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The onl...

Page 109: ... of the device with this command The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers The device sets the BSY bit and sets the following register value After that the device clears the BSY bit and generates an interrupt Power save mode Sector Count register During moving to standby mode Standby mode During returning from t...

Page 110: ...pecified in the FR register is supported the Aborted Command error is posted It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted When the failure prediction feature is disabled the Aborted Command error is posted in response to subcommands other than SMART Enable ...

Page 111: ...X D3 SMART Save Attribute Values When the device receives this subcommand it asserts the BSY bit saves device attribute value data then clears the BSY bit X D8 SMART Enable Operations This subcommand enables the failure prediction feature The setting is maintained even when the device is turned off and then on When the device receives this subcommand it asserts the BSY bit enables the failure pred...

Page 112: ...is below the insurance failure threshold value the device is about to fail or the device is nearing the end of it life In this case the host recommends that the user quickly backs up the data At command issuance I O registers setting contents 1F7H CM 1 0 1 1 0 0 0 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Key C2h Key 4Fh xx xx Subcommand At command completion I O registers setting co...

Page 113: ...e SMART Read Attribute Thresholds subcommand FR register D1h Table 5 9 Format of device attribute value data Byte Item 00 01 Data format version number 02 Attribute 1 Attribute ID 03 04 Status flag 05 Current attribute value 06 Attribute value for worst case so far 07 to 0C Raw attribute value 0D Reserved 0E to 169 Attribute 2 to attribute 30 The format of each attribute value is the same as that ...

Page 114: ...ormat of each threshold value is the same as that of bytes 02 to 0D 16A to 17B Reserved 17C to 1FE Unique to vendor 1FF Check sum Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds The data format version numbers of the device attribute values and insurance failure thresholds are t...

Page 115: ...99 Ultra ATA CRC Error Rate 200 Write error rate 201 to 255 Unique to vendor Status flag Bit 0 If this bit is 1 the attribute is covered by the insurance of the drive when the attribute value exceeds the threshold Bit 1 If this bit is 1 0 the attribute value is updated only by online test offline test Bit 2 If this bit is 1 the attribute value shows the performance Bit 3 If this bit is 1 the attri...

Page 116: ...alues collected to date This value indicates the state nearest to a failure so far Raw attribute value Raw attributes data is retained Failure prediction capability flag Bit 0 The attribute value data is saved to a medium before the device enters power saving mode Bit 1 The device automatically saves the attribute value data to a medium after the previously set operation Bits 2 to 15 Reserved bits...

Page 117: ...g upon the amount of data to be flushed and the success of the operation NOTE This command may take longer than 30 s to complete If the command is not supported the device shall set the ABRT bit to one An unrecoverable error encountered during execution of writing data results in the termination of the command and the error is reported And the test write cache data is removed At command issuance I...

Page 118: ...ssword the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error The section about the SECURITY FREEZE LOCK command d...

Page 119: ...n 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information 31 SECURITY ERASE PREPARE F3h The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command Issuing this command during FR...

Page 120: ... 512 byte data shown in Table 1 1 to the device The device compares the user password or master password in the transferred data with the user password or master password already set The device erases user data invalidates the user password and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the...

Page 121: ...puts the device into FROZEN MODE The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE SECURITY SET PASSWORD SECURITY UNLOCK SECURITY DISABLE PASSWORD SECURITY ERASE UNIT FROZEN MODE is canceled when the power is turned off If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged Issuing...

Page 122: ...on I O registers setting contents 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information 34 SECURITY SET PASSWORD F1h This command enables a user password or master password to be set The host transfers the 512 byte data shown in Table 1 2 to the device The device determines the operation of the lock function according to the specifications o...

Page 123: ...ssword is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password or the master password already set Master High The specified password is saved as a new master password The lock function is not enabled User Maximum The specified password is saved as a new user password The lock function is enabled aft...

Page 124: ... set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the security level in LOCKED MODE is set to the highest level the Aborted Command error is always returned When the user password is selected The password is compared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command erro...

Page 125: ...ontents 1F7H CM 1 1 1 1 0 0 1 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers setting contents 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information ...

Page 126: ...RS V V V V IDENTIFY DEVICE V V V V IDENTIFY DEVICE DMA V 2 V V V V SET FEATURES V V V V SET MULTIPLE MODE V V V V EXECUTE DEVICE DIAGNOSTIC 1 1 1 1 1 V FORMAT TRACK V V V V V READ LONG V V V V V WRITE LONG V V V V V READ BUFFER V V V V WRITE BUFFER V V V V IDLE V V V V IDLE IMMEDIATE V V V V STANDBY V V V V STANDBY IMMEDIATE V V V V SLEEP V V V V CHECK POWER MODE V V V V SMART V V V V V FLUSH CACH...

Page 127: ...o the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector or block of data is available for transfer to the host the device sets DRQ bit and clears BSY bit The drive then asserts INTRQ signal e After detecting the INTRQ si...

Page 128: ...lection INTRQ DRQ Min 30 µs 1 Expanded Command f d d e e c b a Command BSY INTRQ DRDY Parameter write DRQ Data transfer Figure 5 2 Read Sector s command protocol Even if the error status exists the drive makes a preparation setting the DRQ bit of data transfer It is up to the host whether data is transferred In other words the host should receive the data of the sector 512 bytes of uninsured dummy...

Page 129: ...requests the data transfer setting in DRQ bit the correct device operation is not guaranteed Transfers dummy data The host should receive 512 byte dummy data or release the DRQ set state by resetting Status read Command BSY INTRQ DRDY Parameter write DRQ Data transfer Figure 5 3 Protocol for command abort 5 4 2 Data transferring commands from host to device The execution of the following commands ...

Page 130: ...ansferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the DRQ bit g After detecting the INTRQ signal assertion the host reads the Status register h The device resets INTRQ the interrupt signal I If transfer of another sector is requested steps d and after are repeated Figure 5 4 shows an example of WRITE SECTO...

Page 131: ...requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed 5 4 3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device RECALIBRATE SEEK READY VERIFY SECTOR S EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE IDLE IDLE IMME...

Page 132: ...pt processing for the DMA transfer differs the following point a The host writes any parameters to the Features Sector Count Sector Number Cylinder and Device Head register b The host initializes the DMA channel c The host writes a command code in the Command register d The device sets the BSY bit of the Status register e The device asserts the DMARQ signal after completing the preparation of data...

Page 133: ... E056 01EN 5 70 Status read Expanded g f e c d a Command BSY INTRQ DRDY Parameter write DRQ Data transfer DRQ Multiword DMA transfer DMACK DMARQ IOR or IOW 0 1 Word n 1 n Figure 5 6 Normal DMA data transfer ...

Page 134: ...s of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data The highest fundamental frequency on the cable shall be 16 67 million transitions per second or 8 33 MHz the same as the maximum frequency for PIO Mode 4 and DMA Mode 2 Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA Modes the device is ...

Page 135: ...nts 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated 2 The device shall assert DMARQ to initiate an Ultra DMA burst After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE 3 Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP 4 The host shall negate HDMARDY 5 The host shall negate ...

Page 136: ... least tDVH after generating a DSTROBE edge to latch the data 4 The device shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first 5 5 3 3 Pausing an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 4 and 5 6 4 2 for specific timing requirements a Devi...

Page 137: ...ated 3 The device shall release DD 15 0 no later than tAZ after negating DMARQ 4 The host shall assert STOP within tLI after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 5 The host shall negate HDMARDY within tLI after the device has negated DMARQ The host shall continue to negate HDMARDY until the Ultra DMA burst is terminated Ste...

Page 138: ... device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY 4 If the host negates HDMARDY within tSR after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates HDMARDY greater than tSR after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two a...

Page 139: ...assert DIOR CS0 CS1 DA2 DA1 or DA0 until at least tACK after negating DMACK 5 5 4 Ultra DMA data out commands 5 5 4 1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 7 and 5 6 4 2 for specific timing requirements 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated...

Page 140: ...an tCYC for the selected Ultra DMA Mode The host shall not generate two rising or falling HSTROBE edges more frequently than 2 tCYC for the selected Ultra DMA mode 3 The host shall not change the state of DD 15 0 until at least tDVH after generating an HSTROBE edge to latch the data 4 The host shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whicheve...

Page 141: ...c timing requirements 1 The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges 2 The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge The host shall not negate STOP again until after the Ultra DMA burst is terminated 3 The device shall negate DMARQ within tLI after the host asserts STOP The device shall not assert DMARQ again unti...

Page 142: ...s generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than tSR after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and tRFS timing for the host 5 The device shall negat...

Page 143: ...lculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged e At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If ...

Page 144: ... The following table describes recommended values for series termination at the host and the device Table 5 15 Recommended series termination for Ultra DMA Signal Host Termination Device Termination DIOR HDMARDY HSTROBE 33 ohm 82 ohm DIOW STOP 33 ohm 82 ohm CS0 CS1 33 ohm 82 ohm DA0 DA1 DA2 33 ohm 82 ohm DMACK 33 ohm 82 ohm DD15 through DD0 33 ohm Inductor DMARQ 82 ohm 33 ohm INTRQ 82 ohm 33 ohm I...

Page 145: ...er selection setup time for DIOR DIOW 25 ns t2 Pulse width of DIOR DIOW 70 ns t2i Recovery time of DIOR DIOW 25 ns t3 Data setup time for DIOW 20 ns t4 Data hold time for DIOW 10 ns t5 Time from DIOR assertion to read data available 20 ns t6 Data hold time for DIOR 5 ns t9 Data register selection hold time for DIOR DIOW 10 ns t10 Time from DIOR DIOW assertion to IORDY low level 35 ns t11 Time from...

Page 146: ...parameter Min Max Unit t0 Cycle time 120 ns tC Delay time from DMACK assertion to DMARQ negation 35 ns tD Pulse width of DIOR DIOW 70 ns tE Data setup time for DIOR 30 ns tF Data hold time for DIOR 5 ns tG Data setup time for DIOW 20 ns tH Data hold time for DIOW 10 ns tI DMACK setup time for DIOR DIOW 0 ns tJ DMACK hold time for DIOR DIOW 5 ns tK Continuous time of high level for DIOR DIOW 25 ns ...

Page 147: ...ntains the values for the timings for each of the Ultra DMA Modes 5 6 3 1 Initiating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 10 Initiating an Ultra DMA data in burst ...

Page 148: ...E from STOP during a data in burst tLI 0 150 0 150 0 150 Limited interlock time see Note 1 tMLI 20 20 20 Interlock time with minimum see Note 1 tUI 0 0 0 Unlimited interlock time see Note 1 tAZ 10 10 10 Maximum time allowed for output drivers to release from being asserted or negated tZAH 20 20 20 tZAD 0 0 0 tENV 20 70 20 70 20 70 Envelope time from DMACK to STOP and HDMARDY during data in burst i...

Page 149: ...nder to recipient or recipient to sender interlocks that is one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding tUI is an unlimited interlock that has no maximum time value tMLI is a limited time out that has a defined minimum tLI is a limited time out that has a defined maximum 2 All timing parameters are measured at the connector of the ...

Page 150: ... Ultra DMA Modes Note DD 15 0 and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 11 Sustained Ultra DMA data in burst ...

Page 151: ... for each of the Ultra DMA Modes Notes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 If the tSR timing is not satisfied the host may receive zero one or two more data words from the device Figure 5 12 Host pausing an Ultra DMA data in burst ...

Page 152: ...in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 13 Device terminating an Ultra DMA data in burst ...

Page 153: ...in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 14 Host terminating an Ultra DMA data in burst ...

Page 154: ... out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 15 Initiating an Ultra DMA data out burst ...

Page 155: ...ra DMA Modes Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 16 Sustained Ultra DMA data out burst ...

Page 156: ...or each of the Ultra DMA Modes Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 If the tSR timing is not satisfied the device may receive zero one or two more data words from the host Figure 5 17 Device pausing an Ultra DMA data out burst ...

Page 157: ...ut burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 18 Host terminating an Ultra DMA data out burst ...

Page 158: ...in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 19 Device terminating an Ultra DMA data out burst ...

Page 159: ...et 2 Master and slave devices are present 2 drives configuration tP Clear Reset Slave device Master device tN DASP PDIAG BSY BSY DASP tQ tR tS Symbol Timing parameter Min Max Unit tM Pulse width of RESET 25 µs tN Time from RESET negation to BSY set 400 ns tP Time from RESET negation to DASP or DIAG negation 1 ms tQ Self diagnostics execution time 30 s tR Time from RESET negation to DASP assertion ...

Page 160: ...Address Translation 6 3 Power Save 6 4 Defect Management 6 5 Read Ahead Cache 6 6 Write Cache 6 1 Device Response to the Reset This section describes how the PDIAG and DASP signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command ...

Page 161: ...vice is connected After the slave device device 1 releases its own power on reset state the slave device shall report its presence and the result of power on diagnostics to the master device as described below DASP signal Asserted within 400 ms and negated after the first command is received from the host or within 31 seconds or after executing software reset which ever comes first PDIAG signal Ne...

Page 162: ...e master device recognizes that no slave device is connected After the slave device receives the hardware reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below DASP signal Asserted within 400 ms and negated after the first command is received from the host or within 31 seconds or after executing software reset which ever com...

Page 163: ... presence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds then negated within 31 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 31 sec Max 30 sec Max 1 ms If the slave device is p...

Page 164: ...CE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds then negated within 6 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 6 sec Max 5 sec Max 1 ms If t...

Page 165: ...he default translation mode The parameters in Table 6 1 are called BIOS specification Table 6 1 Default parameters MPC3065AH MPC3045AH Number of cylinders 13 456 9 408 Number of head 15 Number of sectors track 63 Formatted capacity MB 6 510 5 4 551 9 As long as the formatted capacity of the IDD does not exceed the value shown on Table 6 1 the host can freely specify the number of cylinders heads a...

Page 166: ...ctor from the last sector of the current physical sector Figure 6 5 shows an example assuming there is no track skew LS 63 LH2 LH1 LH0 LS 2 LS 1 LS 1 243 242 241 190 189 64 63 62 3 2 12 11 1 1 127 126 Physical sector Physical sector ex Zone 0 Physical parameter Physical sector 1 to 241 For the rest 2 spare sectors Specification of INITIALIZE DEVICE PARAMETERS command Logical head LH 0 to 14 Logica...

Page 167: ...hysical sector ex Zone 0 Physical parameter Physical sector 1 to 241 For the rest 2 spare sectors Physical cylinder 0 Physical head 0 SP SP LBA 481 LBA 480 3 2 1 Physical cylinder 0 Physical head 1 LBA 243 LBA 242 LBA 241 243 242 241 240 243 242 Figure 6 6 Address translation example in LBA mode 6 3 Power Save The host can change the power consumption state of the device by issuing a power command...

Page 168: ...he device enters the Idle mode under the following conditions IDLE command or IDLE IMMEDIATE command is issued in the active mode or Standby mode And in case that the following command with accessing the host is issued when the device is in Idle mode the device is still stayed in the Idle mode after processing Reset IDLE command or IDLE IMMEDIATE command A command without accessing the medium 3 St...

Page 169: ...e standby mode is to execute a software or hardware reset The drive enters the sleep mode under the following condition A SLEEP command is issued Issued commands are invalid ignored in this mode 6 3 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE 6 4 Defect Management Defective sectors of which the medium ...

Page 170: ...rnative assignment 1 cylinder drive 6 4 2 Alternating defective sectors The two alternating methods described below are available 1 Sector slip processing A defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector physically adjacent sector to the defective sector When defective sector is present the sector slip processing is performed in...

Page 171: ...ure 6 8 shows an example that cylinder 0 head 0 is at track slip processsing unused unused unused unused unused unused unused unused unused Head 0 SP SP 243 242 241 6 5 4 3 2 1 Cylinder 0 Sector physical Index Head 0 Head 1 SP SP 243 242 241 6 5 4 3 2 1 Track slip 0 6 5 4 3 2 Cylinder 0 Head 0 Sector 1 Cylinder 0 Cylinder 0 Head 0 Sector 241 162 161 5 4 3 2 1 Cylinder 0 Head 0 Sector 1 Head 1 Trac...

Page 172: ...ad 0 Head 0 Already assigned Defective sector 4 alternate cylinders are provided for each head in zone 13 inner side When an access request to sector 5 is specified the device accesses the alternated sector in the alternate cylinder instead of sector 5 When an access request to sectors next to sector 5 is specified the device seeks to cylinder 0 head 0 and continues the processing Defective sector...

Page 173: ... disk medium The host can access the data at higher speed 6 5 1 Data buffer configuration The device has a 512 KB data buffer The buffer is used by divided into three parts for MPU work for auto transfer of write commands for read cache of read commands see Figure 6 10 for R W command for MPU work 480 KB 491 520 bytes 32 KB 32 768 bytes 512 KB 524 288 bytes Figure 6 10 Data buffer configuration Th...

Page 174: ...ET FEATURES command no caching operation is performed 2 Data that are object of caching operation The following data are object of caching operation 1 Read ahead data read from the disk medium in the data buffer after completion of the command that are object of caching operation 2 Data transferred to the host system once by requesting with the command that are object of caching operation But when...

Page 175: ...t only for read DAP HAP 2 Transfers the requested data that already read to the host system with reading the requested data from the disk media Read requested data Stores the read requested data upto this point Empty area DAP HAP 3 After reading the requested data and transferring the requested data to the host system had been completed the disk drive continues to read till the read segment become...

Page 176: ... the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data Empty data Mis hit data 2 The disk drive transfers the requested data that is already read to the host system with reading the requested data Requested data DAP HAP Mis hit data Empty data 3 After completion of the reading and transferring the requested data to the host system the d...

Page 177: ...fers the hit data in the buffer to the host system The disk drive performs the read ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system 1 In the case that the contents of buffer is as follows at receiving a read command Start LBA Last LBA DAP HAP Completion of transferring r...

Page 178: ...which the requested data is stored After completion of command a previously existed cache data before the full hit reading are still kept in the buffer and the disk drive does not perform the read ahead operation 1 In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command the disk drive sets the HAP to the address of which the ...

Page 179: ... the data buffer The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data and reads remaining requested data from the disk media directly Following is an example of partially hit to the cache data Last LBA Cache data 1 The disk drive sets the HAP to the address where the partially hit data is stored and sets the DAP to the addr...

Page 180: ...ansferring partially hit data and reads lack data from the disk media at the same time stopped HAP Requested data to be transferred DAP Partially hit data Lack data 3 The cache data for next read command is as follows Cache data Last LBA Start LBA ...

Page 181: ...The drive generates an interrupt of command complete after completion of data transfer requested by the host system as same as at previous command When the write operation of the previous command had been completed the latency time occurs to search the target sector If the received command is not a sequential write the drive receives data of sectors requested by the host system as same as sequenti...

Page 182: ...n is enabled the transferred data from the host by the WRITE SECTOR S is not completely written on the disk medium at the time that the interrupt of command complete is generated When the unrecoverable error occurs during the write operation the command execution is stopped Then when the drive receives the next command it generates an interrupt of abnormal end However an interrupt of abnormal end ...

Page 183: ...AÑA S A Almagro 40 28010 Madrid SPAIN TEL 34 91 681 8100 FAX 34 91 681 8125 FUJITSU AUSTRALIA LIMITED 2 Julius Avenue Cnr Delhi Road North Ryde N S W 2113 AUSTRALIA TEL 61 2 9776 4555 FAX 61 2 9776 4556 FUJITSU HONG KONG LTD Room 2521 Sun Hung Kai Centre 30 Harbour Road HONG HONG TEL 852 2827 5780 FAX 852 2827 4724 FUJITSU KOREA LTD Coryo Finance Center Bldg 23 6 YoulDo Dong Young DungPo Gu Seoul ...

Page 184: ...of this publication What is your occupation Your other comments may be entered here Please be specific and give page paragraph and line number references where applicable Your Name Return Address Sales Operating Installing Maintaining Learning Reference Fair Poor Very Good Good Very Poor Fully covered Well Illustrated Thank you for your interest Please send this sheet to one of the addresses in a ...

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