Acromag VPX4821A User Manual Download

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Summary of Contents for VPX4821A

Page 1: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

Page 2: ... Carrier USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Email solutions acromag com Copyright 2017 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8501117D ...

Page 3: ...PCIe NT Port Enable Select 8 3 3_AUX Power 9 JTAG Reference Power 9 Clock Settings 9 Reset 10 I2 C PROGRAMMING 10 NVROM 11 LED s 11 BACKPLANE KEY 11 CONNECTORS 11 VPX Connectors 14 PMC Connectors 16 XMC Connectors 20 FIELD GROUNDING CONSIDERATIONS 23 3 VPX CONNECTIVITY 24 VITA 65 PROFILES 24 REAR I O 24 4 SERVICE AND REPAIR 26 SERVICE AND REPAIR ASSISTANCE 26 PRELIMINARY SERVICE PROCEDURE 26 WHERE...

Page 4: ...Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effect...

Page 5: ... an air cooled product which can be used for front and rear I O XMC PMC mezzanine modules Model VPX4821A XX CC LF is an extended temperature conduction cooled product which supports all Acromag FPGA modules It only supports Rear I O Model Description Temp Range VPX4821A 42 LF Air cooled 6U VPX XMC PMC Carrier for Data Plane with VITA 42 0 to 70 C VPX4821A 42 CC LF Conduction cooled 6U VPX XMC PMC ...

Page 6: ...lso run off only the VPX PS3 5V supply Please contact the factory for details All AUX supplies are optional and are only required if used by the XMC PMC modules JTAG Programming Header The VPX4821A carrier includes a programming connector that mates with a Xilinx programmer for programming Acromag FPGA products Acromag XMC FPGA boards can be configured to route the JTAG programming signals through...

Page 7: ...ically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power The board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power requirements Be sure that the system power supplies are ab...

Page 8: ...e factory default setting For rugged designs all jumpers can be replaced with 0 Ohm resistors Please contact the factory for details PCIe Lane Configuration The VPX P1 PCIe lane configuration is selectable via the J1 jumper Please note that these strapping settings can be overwritten via a I2 C write to the PEX8734 Table 2 1 PCIe Lane Jumper Configuration PCIe Lane Configuration J1 Jumper Configur...

Page 9: ... O S O O Port 3 O O S O S O Default setting is Port 0 with vertical J3 jumbers 1 3 and 5 7 set Fan Out Enable Enable peer to peer Downstream endpoint to Downstream endpoint traffic with jumper J5 9 10 set If peer to peer Downstream endpoint to Downstream endpoint traffic is not needed this jumper can be left open Table 2 4 Fan Out Enable Jumper Setting Fan Out Enable J5 9 10 Enable SET Disable OPE...

Page 10: ...use damage to either the board or chassis power supply Default setting is 3 3V_AUX from Backplane with horizontal J6 7 8 jumber set JTAG Reference Power The pull up voltage on the JTAG pins to XMC P15 and P25 can be selected as either 2 5V or 3 3V Refer to the XMC User s Manual for proper voltage selection The jumper J3 9 10 is for slot A and the jumper J1 9 10 is for slot B Table 2 7 JTAG Power S...

Page 11: ...t When enabled the VPX SYSRESET signal will be held down on power up for a configurable amount of time This can be used to allow extra time for a particularly large FPGA program to load before reset is de asserted and the PCIe bus is enumerated for instance Refer to the table below for jumper settings Table 2 9 Reset Output Generator Jumper Settings Reset Output Generator J6 1 2 J6 3 4 System Rese...

Page 12: ... has connected DS8 Red PMC B Only PCIe Lane 3 has connected DS9 Red PMC B Only PCIe Lane 4 has connected DS10 Green VPX PCIe Port 0 has successfully connected DS11 Green VPX PCIe Port 1 has successfully connected DS12 Green VPX PCIe Port 2 has successfully connected DS13 Green VPX PCIe Port 3 has successfully connected DS14 Green A Connection has been made to XMC PMC Slot A DS15 Green A Connection...

Page 13: ...J14 J25 PMC user signals Rear I O J15 J25 XMC PCIe signals J16 J26 XMC user signals Rear I O P0 VPX Power and system signals P1 VPX Data Plane This connects to all PCIe lanes P2 VPX Expansion plane This connector is not populated P3 P4 PMC XMC Slot A Rear I O P5 P6 PMC XMC Slot B Rear I O ...

Page 14: ...CARRIER CARD SERIES VPX4821A XMC PMC CARRIER 13 Figure 3 Connector Locations ...

Page 15: ...L2_TXP PCIE_L2_TXN Gnd 4 Gnd PCIE_L3_RXP PCIE_L3_RXN Gnd PCIE_L3_TXP PCIE_L3_TXN Gnd 5 PCIE_L4_RXP PCIE_L4_RXN Gnd PCIE_L4_TXP PCIE_L4_TXN Gnd 6 Gnd PCIE_L5_RXP PCIE_L5_RXN Gnd PCIE_L5_TXP PCIE_L5_TXN Gnd 7 PCIE_L6_RXP PCIE_L6_RXN Gnd PCIE_L6_TXP PCIE_L6_TXN Gnd 8 Gnd PCIE_L7_RXP PCIE_L7_RXN Gnd PCIE_L7_TXP PCIE_L7_TXN Gnd 9 PCIE_L8_RXP PCIE_L8_RXN Gnd PCIE_L8_TXP PCIE_L8_TXN Gnd 10 Gnd PCIE_L9_RX...

Page 16: ..._RIO25_P Gnd PMC1_RIO24_N PMC1_RIO24_P Gnd 14 Gnd PMC1_RIO27_N PMC1_RIO27_P Gnd PMC1_RIO26_N PMC1_RIO26_P Gnd 15 PMC1_RIO29_N PMC1_RIO29_P Gnd PMC1_RIO28_N PMC1_RIO28_P Gnd 16 Gnd PMC1_RIO31_N PMC1_RIO31_P Gnd PMC1_RIO30_N PMC1_RIO30_P Gnd All blue colored cells are Not Used in this design Table 2 14 P4 XMC SLOT A Rear I O Pin A B C D E F G 1 XMC1_DP05_N XMC1_DP05_P Gnd XMC1_DP04_N XMC1_DP04_P Gnd...

Page 17: ...C2_RIO27_N PMC2_RIO27_P Gnd PMC2_RIO26_N PMC2_RIO26_P Gnd 15 PMC2_RIO29_N PMC2_RIO29_P Gnd PMC2_RIO28_N PMC2_RIO28_P Gnd 16 Gnd PMC2_RIO31_N PMC2_RIO31_P Gnd PMC2_RIO30_N PMC2_RIO30_P Gnd All blue colored cells are Not Used in this design Table 2 16 P6 XMC SLOT B Rear I O Pin A B C D E F G 1 XMC2_DP05_N XMC2_DP05_P Gnd XMC2_DP04_N XMC2_DP04_P Gnd 2 Gnd XMC2_DP07_N XMC2_DP07_P Gnd XMC2_DP06_N XMC2_...

Page 18: ...9 29 5V 30 3 3V 31 AD17 32 FRAME 33 GND 34 GND 35 IRDY 36 DEVSEL 37 5V 38 PCIXCAP 39 LOCK 40 NC1 41 NC1 42 PAR 43 GND 44 3 3V 45 AD15 46 AD12 47 AD11 48 AD9 49 5V 50 GND 51 C BE0 52 AD6 53 AD5 54 AD4 55 GND 56 3 3V 57 AD3 58 AD2 59 AD1 60 AD0 61 5V 62 GND 63 REQ64 64 1 NC Not used Table 2 18 Jx2 PMC PCI Signals Pin Description Number Pin Description Number 12V 1 TRST 2 TMS 3 TDO 4 TDI 5 GND 6 GND ...

Page 19: ...3 GND 44 AD14 45 AD13 46 M66EN 47 AD10 48 AD8 49 3 3V 50 AD7 51 NC1 52 3 3V 53 NC1 54 NC1 55 GND 56 NC1 57 NC1 58 GND 59 NC1 60 ACK64 61 3 3V 62 GND 63 NC1 64 1 NC Not used Table 2 19 Jx3 PMC PCI Signals Pin Description Number Pin Description Number NC1 1 GND 2 GND 3 C BE7 4 C BE6 5 C BE5 6 C BE4 7 GND 8 3 3V 9 PAR64 10 AD63 11 AD62 12 AD61 13 GND 14 GND 15 AD60 16 AD59 17 AD58 18 AD57 19 GND 20 3...

Page 20: ... 2 20 Jx4 PMC PCI Rear I O Signals Pin Description Number Pin Description Number RIO0_P 1 RIO1_P 2 RIO0_N 3 RIO1_N 4 RIO2_P 5 RIO3_P 6 RIO2_N 7 RIO3_N 8 RIO4_P 9 RIO5_P 10 RIO4_N 11 RIO5_N 12 RIO6_P 13 RIO7_P 14 RIO6_N 15 RIO7_N 16 RIO8_P 17 RIO9_P 18 RIO8_N 19 RIO9_N 20 RIO10_P 21 RIO11_P 22 RIO10_N 23 RIO11_N 24 RIO12_P 25 RIO13_P 26 RIO12_N 27 RIO13_N 28 RIO14_P 29 RIO15_P 30 RIO14_N 31 RIO15_N...

Page 21: ...n Slot XMC Connectors Table 2 21 Jx5 XMC PCIe Signals Pin Description Number Pin Description Number PET0p0 A1 PET0p1 D1 GND A2 GND D2 PET0p2 A3 PET0p3 D3 GND A4 GND D4 PET0p4 A5 PET0p5 D5 GND A6 GND D6 PET0p6 A7 PET0p7 D7 GND A8 GND D8 NC A9 NC D9 GND A10 GND D10 PER0p0 A11 PER0p1 D11 GND A12 GND D12 PER0p2 A13 PER0p3 D13 GND A14 GND D14 PER0p4 A15 PER0p5 D15 GND A16 GND D16 PER0p6 A17 PER0p7 D17 ...

Page 22: ...3 3V C3 VPWR F3 TCK C4 MRSTO 1 F4 3 3v C5 VPWR F5 TMC C6 12V F6 3 3v C7 VPWR F7 TDI C8 12V F8 NC C9 VPWR F9 TDO C10 GA0 F10 MBIST C11 VPWR F11 GA1 C12 MPRESENT F12 3 3V AUX C13 VPWR F13 GA2 C14 MSDA F14 NC C15 VPWR F15 MVMRO C16 MSCL F16 NC C17 NC F17 NC C18 NC F18 NC C19 NC F19 Table 2 22 Jx6 XMC Rear I O Signals1 Pin Description Number Pin Description Number DP00_P A1 DP01_P D1 GND A2 GND D2 DP0...

Page 23: ...B3 DP03_N E3 GND B4 GND E4 DP04_N B5 DP05_N E5 GND B6 GND E6 DP06_N B7 DP07_N E7 GND B8 GND E8 DP08_N B9 DP09_N E9 GND B10 GND E10 DP10_N B11 DP11_N E11 GND B12 GND E12 DP12_N B13 DP13_N E13 GND B14 GND E14 DP14_N B15 DP15_N E15 GND B16 GND E16 DP16_N B17 DP17_N E17 GND B18 GND E18 DP18_N B19 DP19_N E19 User_SEU1 C1 NC F1 User_SEU2 C2 NC F2 NC C3 NC F3 NC C4 NC F4 NC C5 NC F5 NC C6 NC F6 NC C7 NC ...

Page 24: ...rovided on the XMC module itself the field I O connections are not isolated from the PCIe bus Care should be taken in designing installations without isolation to avoid ground loops and noise pickup This is particularly important for analog I O applications when a high level of accuracy resolution is needed 12 bits or more Contact your Acromag representative for information on our many isolated si...

Page 25: ...ane as well as managing the interconnect between boards All the PCIe lanes are connected to P1 the data plane Further information can be found in VITA 65 REAR I O The Rear is mapped per VITA 46 9 method P64s X12d X8D This mapping is shown in the diagram on the following page Note per the errata attached to VITA 46 9 that the polarity of the XMC twisted pairs is reversed compared to the VITA 42 spe...

Page 26: ...CARRIER CARD SERIES VPX4821A XMC PMC CARRIER 25 Figure 4 6U Carrier P64s X12d X8d Mapping Diagram ...

Page 27: ...ard to verify that it is correctly configured Replacement of the carrier and or XMC PMC with one that is known to work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at https www acromag com Our web site co...

Page 28: ...V_AUX 12V_AUX The 5V and 3 3V supplies for the XMC PMC modules are generated by on board DC DC converters from the 12V backplane supply Currents specified are for the carrier board only for Model VPX4821A add the XMC module currents for the total current required from each supply The major power components are listed below to assist with power calculations Table 5 1 VPX4821A Internal Power usage t...

Page 29: ...1A 0 05A NA 1 12V From backplane Assume 6A available 72W to generate 3 3 5 0V supplies 2 Derating is required above this temperature due to DC DC See Power dissipation section below Note that extra allowance of 0 5A is available on the CC modules due to the addition of a heat sink Power Dissipation Power dissipation is a complicated issue on the carrier card The maximum allowable die temperature i...

Page 30: ...the temperature and power usage specified and MUST be connected to the midplane on conduction cooled frame for maximum effectiveness The two charts below give the maximum power dissipation per slot for both air cooled and conduction cooled boards For air cooled boards it is assume air flow of at least 200cfm across the module Conduction cooled conditions assume a 6U Conduction cooled chassis with ...

Page 31: ...al rates exceed the rated bandwidth of the XMC connectors While testing to Gen2 signals was completed Acromag cannot certify Gen2 compliance with non Acromag products Switch A PLX Tech PEX8734 Gen 2 0 PCIe switch is used for the routing of PCIe signals Maximum PCIe trace length on XMC module 500mils Recommended for Gen2 compliance 0 5 10 15 20 25 30 0C 50C 65C 70C Power W per slot Air Cooled Power...

Page 32: ... O is compliant to VITA 46 9 Slot A is mapped P3w1 P64s P4w1 X12d X8d Slot B is mapped P5w1 P64s P6w1 X12d X8d ENVIRONMENTAL ENVIRONMENTAL Operating Temperature VPX4821A XX LF 0 to 70 C VPX4821A XX CC LF 40 C to 85 C Max card edge temp 85 C Relative Humidity 5 95 non condensing Storage Temperature 55 to 100 C EMC Compliance Radiated Field Immunity Designed to comply with IEC61000 4 3 class A Surge...

Page 33: ...are lost when power is removed Yes No Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed Yes No Type EEPROM Flash etc EEPROM Size 2kb User Modifiable Yes No Function Storage of Code IPMI information Process to Sanitize Clear Memory by erasing Note device is empty when first shipped Type EEPROM Flash etc EEPROM Size 4096x...

Page 34: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

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