ZiLOG Z8 CPU, User Manual

Page: 97 / 261

Z8
®
CPU
User Manual
UM001604-0108 Counters and Timers
90
Gated Internal Clock Mode
The T
IN
Gated Internal Clock Mode (TMR bit 5 and bit 4 set to 0 and 1 respectively) mea-
sures the duration of an external event. In this mode, the T1 prescaler is driven by the
internal timer clock, gated by a High level on T
IN
(see Figure 83 ). T1 counts while T
IN
is
High and stops counting while T
IN
is Low. Interrupt request IRQ2 is generated on the
High-to-Low transition of T
IN
signalling the end of the gate input. Interrupt request IRQ5
is generated if T1 reaches its end-of-count.
Triggered Input Mode
The T
IN
Triggered Input Mode (TMR bits 5 and 4 are set to 1 and 0, respectively) causes
T1 to start counting as the result of an external event (see Figure 84 on page 91). T1 is then
loaded and clocked by the internal timer clock following the first High-to-Low transition
on the T
IN
input. Subsequent T
IN
transitions do not affect T1. In SINGLE-PASS mode, the
Enable bit is reset whenever T1 reaches its end-of-count. Further T
IN
transitions have no
effect on T1 until software sets the Enable Count bit again. In CONTINUOUS mode, once
Figure 82. External Clock Input Mode
Figure 83. Gated Clock Input Mode
D
P3
1
Internal
IRQ
2
TMR
T
IN
Clock
D
PRE1 T1
IRQ
5
D
5
–D
4
= 00
Clock
OSC
÷
2
÷
4
D D
PRE1
P3
1
T1
IRQ
2
T
IN
IRQ
5
Gate
Internal
TMR
D
5–
D
4 =
01
Clock