UM012811-0904
eZ8 CPU Instruction Set Description
eZ8 CPU
User Manual
190
TMX
Test Under Mask using Extended Addressing
TMX dst, src
Operation
dst AND src
Description
This instruction tests selected bits in the destination operand for a logical 0 value. Specify
the bits to be tested by setting a 1 bit in the corresponding bit position in the source oper-
and (the mask). The TMX instruction AND’s the destination with the source operand
(mask). Check the Zero flag to determine the result. If the Z flag is set, the tested bits are
0. When a TMX operation is completed, the destination and source operands retain their
original values.
Flags
Attributes
Escaped Mode Addressing
Using Escaped Mode Addressing, address mode ER for the source or destination can spec-
ify a Working Register with 4-bit addressing.
If the high byte of the source or destination address is
EEH
(11101110B), a Working Regis-
ter is inferred. For example, the operand
EE3H
selects Working Register R3. The full 12-
bit address is given by {RP[3:0], RP[7:4], 3H}.
To access Registers on Page EH (addresses E00H to EFFH), set the Page Pointer, RP[3:0],
to
EH
and set the Working Group Pointer, RP[7:4], to the desired Working Group.
C
Unaffected.
Z
Set if the result is zero; reset otherwise.
S
Set if the result is negative; reset otherwise.
V
Reset to 0.
D
Unaffected.
H
Unaffected.
Mnemonic Destination, Source
Opcode (Hex)
Operand 1
Operand 2
Operand 3
TMX
ER1, ER2
78
ER2[11:4]
{ER2[3:0], ER1[11:8]} ER1[7:0]
TMX
ER1, IM
79
IM
{0H, ER1[11:8]}
ER1[7:0]
