Mainboard User's Manual
Page 29
BIOS
Setup
CPU to PCI Write Buffer
When this field is Enabled, writes from the CPU to the PCI bus are
buffered, to compensate for the speed differences between the CPU
and the PCI bus. When Disabled, the writes are not buffered and the
CPU must wait until the write is complete before starting another write
cycle. The choice: Enabled, Disabled.
PCI Dynamic Bursting
This item allows you to enable or disable the PCI dynamic bursting
function. The choice: Enabled, Disabled.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait states.
The choice: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1. The choice: Enabled, Disabled.
PCI#2 Access #1 Retry
When disabled, PCI#2 will not be disconnected until access finishes
(default). When enabled, PCI#2 will be disconnected if maximum retries
are attempted without success. The choice: Enabled, Disabled.
AGP Master 1 WS Write
When Enabled, writes to the AGP(Accelerated Graphics Port) are
executed with one wait states. The choice: Enabled, Disabled.
AGP Master 1 WS Read
When Enabled, read to the AGP(Accelerated Graphics Port) are
executed with one wait states. The choice: Enabled, Disabled.
