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Mainboard User's Manual
Advanced Chipset Features
DRAM Timing By SPD
This item allows you to Enable or Disable the Auto configuration
function of DIMM by reading the SPD ROM information. If problem
appears after Enabling this option. Please power off the system, and
clear the CMOS, power on the system again and "Load Optimized
Default".
DRAM Clock
This item allows you to control the DRAM speed.
The choice: 100MHz, 133MHz.
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
The choice: 2, 3.
Bank Interleave
Set this option to enabled the DRAM banks interleave logic. The
setting are 2 bank, 4 bank, Disabled. The optimal and fail - safe
default setting on disabled.
