ZETRON 4010, Service Manual

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Model 4010 Radio Dispatch Console Service Manual
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From the Dual Channel Card’s daughter board connector J1, the DTMF decode circuit interfaces the
receive audio (RX) signal. This signal goes to amplifier U4B and to the AIN input of U1, the DTMF
decoder. When a valid DTMF signal is detected, the DV output high and clocks the latch U2B.
When the microprocessor reads the status of the card with the SPI bus, the ENCH signal goes high
and generates a load (LD) signal to U6. U6 will read the output of U2B (the latched DV signal) and
the DTMF decoded digits of U1. The SPI clock (SCLK*) will shift out the latched data on the
DATA line. The SCLK* signal will also clear the latched DV signal (U2B).
The RX signal also goes to an internal amplifier input AIN of U5. U5 is a band pass, switched capa-
citor filter that is tuned for a center frequency of 2175Hz at the CMOS and RC inputs. The C8, R15,
R14, and R16 form the tuning circuit. When a high level guard tone at 2175Hz is passed through the
filter, the amplifier U4A forms a peak detector to the input of U3A. The holding capa-citor C5 will
hold the detected peaks and provide a steady-state signal at U3B. With JP1 in position A, the signal
will drive Q1 and the LOTL LED on the back panel and the feedback FET Q2. Q2 will lower the
impedance in the input amplifier U4A and increase the gain. The gain will increase 30dB so the
amplifier will keep locked on the low level guard tone signal. The LOTL* output to the channel card
will remain low until the guard tone signal is dropped.
INDIVIDUAL CHANNEL 5-TONE ANI DECODER (950-9707, 950-9708)
The Channel 5-Tone ANI Decoder Board will monitor the receive audio signal and decode either
ZVEI (950-9707) or CCIR/EEA (950-9708) tone received on the channel it is installed on. Both
options use the same circuit board (schematic 008-0147, BOM 702-0147). They differ only in the
software installed.
From the Dual Channel Card’s daughter board connector J1, the receive audio RX signal goes
through amplifier U4A, through a high-pass RCF filter (R3, C6), and to the 5-tone detector U2.
When a valid tone is detected, U2 generates the IRQ output, which generates an interrupt on U1. The
U1 microcontroller, a 68HC05 derivative, reads the tone from the decoder using the serial bus that
connects the two chips (signals SERCLK, COMMAND, REPLY, and CS). After some additional
processing to validate the tone, the microcontroller sends the tone to the M4010 main board using
the SPI bus, signals SCLK*, ENCH*, and D0 signals.
INDIVIDUAL CHANNEL FSK ANI DECODER (950-9709)
The Channel FSK ANI Decoder Board will monitor the receive audio signal and decode the FSK
tones received on the channel it is installed on. The schematic for the board is 008-9583.
From the Dual Channel Card’s daughter board connector J1, the receive audio RX signal goes
through amplifier U7A and to the 5-tone detector U3 (U2 and U4 are not installed). When a valid
FSK pattern is detected, U3 will generate the RXSYN output, which is synchronous internally to the
incoming data. This signal connects to Q1, which generates the IRQ* interrupt to U1. The U1 pro-
cessor, 68HC05, will read the data on D4 and the carrier detect signal on D5 and place the data in the
internal SPI bus register. The main microprocessor will read the information with the SCLK*,
ENCH* and D0 signals.
INDIVIDUAL CHANNEL GE-STAR ANI DECODER (950-9625)
The Channel GE-Star ANI Decoder Board will monitor the receive audio signal and decode the tones
received on the channel it is installed on. The schematic for the board is 008-9741.
From the Dual Channel Card’s daughter board connector P1, the receive audio RX signal goes
through amplifier U7B, the wave shaping circuits of U6 and the U5 comparater. The output of U5 is
the IRQ interrupt to U2, 68HC05 microprocessor. U2 will convert the data into the ANI digits and
place the data in the internal SPI bus register. The main microprocessor will read the information
with the SCLK*, ENCH* and D0 signals.