ZETRON 4010, Service Manual

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Model 4010 Radio Dispatch Console Service Manual
10
The microprocessor uses devices selects to communicate with the components on the bus which are
generated by the port outputs PG7 through PG4. PG4 is used to generate the other devices selects of
U32. These selects control the I/O ports on the data bus.
The timing circuits of U20 and U18 take the 8MHz signal from the microprocessor and divide the
clock down to 4 MHz, 500 kHz, and 9615X16 Hz. The U40 UART used the 9615X16 clock to
generate the RS232 baud rate.
The LOOP IN and LOOP OUT connectors J13, J14, and J15 are used for expansion panels, console
parallel status, and programming the console. These connectors are driven by U45, a RS232 driver
which generates its own + and – 10 volts for drive voltage. The 68B50 UART, U40, sends and
receives the serial data and generates the IRQ* interrupt to the microprocessor.
The auxiliary input connector, P8, connects the general purpose inputs to the buffer U43. The micro-
processor reads this port with the SICS* device select. The auxiliary output connector, P7, contains
four open collector transistor outputs, U42, and four relay contact outputs, K2 through K5. U39 is an
eight bit latch which latches the signal from the microprocessor using device select POR*.
The various PTT and hook switch signals in the system are the inputs of U16 and U19. The micro-
processor monitors U16 and U19 to determine which audio source the operator wants to use. On
sheet 3, U24 is a latch for steering the audio sources. The latched outputs of U24 drive U22, 74C906,
which translates the 5V logic levels into 12V signals to drive the various audio switches.
The device selects (on sheet 3) for the SPI bus components is generated by CHSEL* and U36, U37
and U28. There 16 selects generated, CHEN0* to CHEN14* and the select to HC05. Each CHEN
signal will enable the bidirectional communication bus for that channel. The SPI bus consists of the
microprocessor signals D0 (data out), DI (data in) and the SCK* (500 kHz synchronous clock).
The 68HC705 (HC05) microprocessor of the schematic, generates all the tones (except for guard
tones) that are required in the console. The commands to the HC05 are through the SPI bus. The
tones are generated by the 8-bit output port PA, which has its data, latched into U14 by PB0. The
output of the latch goes through a resistor ladder network to U7. U7 is a low pass filter which goes to
a selectable volume control R62 to the tone bus driver U1. The tone bus goes to the channel card
interfaces.
The input power is on connector J5. The nominal voltage is 13.5 VDC. An alternate source (battery
backup) can be connected to J16. When the primary power is present, K1 is energized and a series of
diodes are connected to J16. This ensures the battery voltage is below the primary power source to
prevent a battery drain. When primary power is not present, K1 is released, and the series diodes are
no longer in series with the battery. Regulator VR3 provides the 5Vdc for the system. VR2 provides
the 5Vdc analog reference voltage and VR1 provides the 10Vdc analog power. R95, C98, R96, C88,
and U44A provide a filter and a low impedance source for the analog reference.
Each of the audio amplifiers (sheet 4) for the desk microphone (U1A and R70), the headset micro-
phone (U6B and R68) and the gooseneck microphone (U6A and R69) have an input adjustment
potentiometer before being routed to the multiplexer U12. The fourth input comes from the HC05
tone generator through the adjustment potentiometer R67. The audio switches of U24 con-trol the
audio steering to U8A. U8A forms a 30dB AGC circuit whose output goes to the MIC BUS through
U4B and to headset sidetone through U8B.
The select bus and unselect bus are the summing node of amplifiers U5B and U5A. The amplifier
U10A is the summing node for the patch bus. The select audio goes through the switch U9A-3 to the
buffer U10B, through the switch U9C-13 to the buffer U2A. This signal drives the select input of the
Display Board. The unselect audio takes a similar path through U9B-1, U2B and to the Display
Board. The select audio and unselect audio also are summed into amplifier U3A along with the Mic
Bus. U3A drives the COMB AUDIO OUT signal on P1, the Auxiliary Audio connector, and ampli-
fier U3B. The output of U3B goes through a peak detector circuit and forms the VU input for the
microprocessor’s analog to digital converter.
The AUXAUD input from P1 is an alternate source of audio that can be summed into the MIC BUS.
The input is optionally terminated with 600 ohms by JP5 and amplitude adjusted by R63. The source
is controlled by audio switch U11A and through the buffer U4A is sent to the summing node of U4B.
DISPLAY BOARD (702-9378)
The Display board contains the LCD display and the amplifier circuits for the select and unselect
speakers. The microprocessor has a bidirectional data path using U39 to drive the interface connector
P11. The read or writing to the LCD is controlled by LCDE, W/R* and A0 signals on P11. The LCD
display, DS1 on the Display Board, is capable of displaying two rows of 16 ASCII characters. R21 is
used to adjust the display’s viewing angle and contrast. JP2 is used to set the brightness of the
display. The three settings of JP2 change the display’s backlight current from 120mA to 45mA and
to 15mA.
The select audio from U2-1 and the unselect audio from U2-7 on the Control Board are sent to the
interface connector P11. Both amplifier circuits work identically. The select circuit has R33 to adjust
the audio level to the amplifier. R32 adjust the minimum audio level that R33 can be set to. R32 can
be set to no audio. The push/pull amplifier circuit can deliver up to 5 watts to the speaker. The output
of U4 is fed to the inverting input of U5 through R27. R34 is used to adjust the output DC level of
U5 for 0 Vdc across the speaker connector JP3.
KEYBOARD (702-9379)
The system keypad and channel keypad of the M4010 are sequentially scanned by the micropro-
cessor at a 50-millisecond interval. The scanning matrix is set up with U33 and U25 latches. P10 is
the interface connector for the hex keypad and system keys.
The C0 to C6 latched signals are presented through P10 (renamed to Rx and Sx) to U3 and U4 on the
Keypad Board. U3 and U4 outputs set the appropriate signal levels to the switch matrix. The indivi-
dual switch status is on the COM1 output of U3, which the microprocessor reads during each matrix
cycle.