Zenith LX-140, Service Manual

Page: 44 / 47

- 2-46 -
■
IC504 M12L16161A
1)
Synchronous DRAM
• PIN Definitions
PIN NAME INPUT FUNCTION
CLK System Clock Active on the positive going edge to sample all inputs.
CS Chip Select Disables or enables device operation by masking or enabling all
inputs except CLK, CKE and L(U)DQM.
CKE Clock Enable Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0~A10/AP Address Row/column addresses are multiplexed on the same pins.
Row address: RA0 ~ RA10, column address : CA0~CA7
BA Bank Select Address Selects bank to be activated during row address latch time.
Selects bank for read/write durring column address latch time.
RAS Row Address Strobe Latches row addresses ont eh positive going edge of the CLK
with RAS low.
CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access.
WE Write Enable Enalbes write operation and row precharge.
Latches data in starting form CAS, WE active.
L(U)DQM Data Input/Output Mask Makes data output Hi-z, tSHZ after the clock and masks the out-
put. Blocks data input when L(U) DQM active.