Zenith H-100 Service Manual Download

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Summary of Contents for H-100

Page 1: ...tion 5 Disk Controller and Drives ADD Part II to Section 5 This is new data for the H 207 Floppy Disk Controller Board CHANGE the following Page 2 99 Parts Required Part number of the programming plug...

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Page 3: ...r cables These extender cables allow you to spread out the H Z 100 over a 29 x 46 surface This permits you to easily reach every Ie while the unit is operating PARTS REQUIRED 2 99 10 82 Qty 2 1 4 20 f...

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Page 5: ...the RESET line at U236 11 is pull ed low A Sc hm it t tr igger shape s this signal and the clock circuits retimes it before applying it to the 8088 READY Pin 22 Ready This is an acknowledgement signal...

Page 6: ...3 22 IML 51lL Sllf IHT ISWAP PORTI 01 l L IIl4Cll O h q P tt A L JT tI P 04 P st D 11 H U 2 OJ lS 44J ItI L D _ 7 I MOL 1111 F r II I IlEF IW PROCESSOR SWAP PORT MBl...

Page 7: ...acing a logic zero on U181 12 and a l c one on U181 2 On the first positive transition of 85 the 85HOLD line will go low enabling the 8085 CPU On the first positive transition of the 88HOLD line will...

Page 8: ...0 pHLOA line to logic one at U180 9 The board that generated the HOLD request can now take control of the H Z 100 SWAP TIMING The 88SEL line also goes to U188 4 a quad D type latch This circuit is des...

Page 9: ...3 25 10 82 SWITCHING FROM 8085 to 8088...

Page 10: ...s logic one into U188 2 the Q1 output at B The next clock pulse causes the Q2 output to latch high shown at C This tri states U200 through the exclusive DR gate at U203B At the same time Q2 goes low t...

Page 11: ...inputs are now the same state U203 11 goes to logic zero to preset both HOLD latches at U187 Both CPUs respond by going into a HOLD stat and sending hold acknowledge signals to U186 the 8088 to pin 3...

Page 12: ...ts are sent to the 8085 maskable through U189A non maskable through U189D The 8SEL line which is the complement of 5SEL disables U1898 and U189C the AND gates to the 8088 Later when the 8085 hands con...

Page 13: ...and the middle 64K of RAH are unchanged This configuration alay also be used for HP H while running the 8085 CPU Confisuration 14 HAPSELl 1 HAPSELO 1 In this configuration 56K in bank 0 appears to be...

Page 14: ...179 5A1 P B V t 82 129 P 5 Af 12 P p 3 c I p BA2 1 P P 1 1 P P 4 H 100E C 4 P 3 _1 21 P P 1 U157 Gl 5 p P 2 I P 2 A P P q P PJ 03 7 p P 1 A 7 39 2 lolll4 1JI P s 43 U C 1 CE2 G2 11 H _ _iJ 4 Pl A _ p...

Page 15: ...71 1 U180 10 L MS1 U186 17 U186 3 H MS1 U2ll 30 U186 4 L MS1 U171 5 U186 l6 L MS 1 U186 3 U186 17 L MS1 U186 4 U186 l8 H MS1 U186 is defective U187 2 H MS1 U186 l8 U187 3 p MS1 Restore U186 5 and go t...

Page 16: ...186 5 to 5 volts 3 Apply power and perform the following tests CHECK S 100 21 H U 171 5 H U180 9 L MS1 MS1 MS1 IF NOT OKAY CHECK U215 3 U171 3 U171 2 U171 1 U180 10 Go to Swap Test 3 U171 1 H U171 2 H...

Page 17: ...U203 13 L MB1 Restore U186 4 and U186 5 and go to CLOCK CIRCUITS TESTS U210 38 H MB1 U210 39 U210 39 H MB1 U181 9 U211 30 L MB1 U211 31 U211 31 L MB1 U187 5 U215 2 H MB1 Restore U186 4 and U186 5 and...

Page 18: ...ns 2 8 9 10 11 12 and 19 SWAP TEST 4 1 Remove the jumper between ground and pin 5 2 Connect the jumper from pin 5 to 5 volts CHECK U180 9 H End of tests U180 10 H U186 13 H U186 17 H U186 18 H MB1 MB1...

Page 19: ...U188 74LS175 HE 443 752 U228 781 12 12V regulator HE 442 644 connector 10 pin connector HE 432 903 U189 741 S08 HE 443 780 U229 791 12 12V regulator HE 442 646 20 pin connector HE 432 1227 2764 ROI1...

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Page 21: ...ON 5 1 CIRCUIT DESCRIPTION 5 5 DISASSEMBLY 5 25 VISUAL CHECKS 5 29 ADJUSTMENTS 5 35 TROUBLESHOOTING 5 39 PARTS LIST 5 49 CIRCUIT BOARD X RAY VIEW 5 53 48 TPI DISK DRIVE DATA 5 57 PART II H 207 INTRODU...

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Page 23: ...CIRCUIT DESCRIPTION 5 125 DISASSEMBLY 5 145 VISUAL CHECKS 5 151 ADJUSTMENTS 5 155 TROUBLESHOOTING 5 165 PARTS LISTS 5 177 CIRCUIT BOARD X RAY VIEW 5 181 CALIBRATION BOARD SCHEMATIC 5 185...

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Page 25: ...PART I INTRODUCTION...

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Page 27: ...PART II INTRODUCTION...

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Page 29: ...cts the type of drive used and the density of the media However present Heath Company software limits the number of drives to three The H 207 can be operated in three different modes Wait State Polled...

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Page 31: ...SPECIFICATIONS...

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Page 33: ...onds per track or faster 8 Single double sided single double density Interface type Shugart 850 or equivalent Data Separator Phase locked loop Precompensation Variable independently for both 5 1 4 and...

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Page 35: ...INTRODUCTION CLOCK SPEED INTERRUPT JUMPERS SLIDE SWITCH DS1 OUTPUT CONNECTORS 5 Disk Drive Connector 8 Disk Drive Connector OPERATION 5 121 5 121 5 122 5 122 5 124 5 124 5 124...

Page 36: ...5 120 N J...

Page 37: ...jumpering at J1 As received J1 is jumpered by a foil run on the bottom of the board See illustration below This jumpering enables the H 207 to operate in computers that have a CPU clock speed faster...

Page 38: ...lled in these locations when the H 207 is used in a HlZ 100 These jumper locations are only used when the H 207 is installed in computers that require interrupt protocol The configuration of the jumpe...

Page 39: ...bits in this block select 1797 registers the control latch or the status port The H Z 100 computer series place the H 207 at port address BOH A map of the I O port is shown below I O ADDR Binary JlEAD...

Page 40: ...E CONNECTOR PI This 50 pin connector provides the necessary signals to drive an 8 Shugart compatible disk drive Refer to the pic tori al at the left for a description of the pinouts of this connector...

Page 41: ...CPU Controller Logic 5 130 Read Status Latch U31 5 130 Read Status Register of 1797 U22 5 131 Write Control Latch U30 5 132 Write Control Register in the 1797 U22 5 133 Data Read Write Operations 5 1...

Page 42: ...J PORT L c C U 0 u J t z c 00 V u J L CONTROL C LATCH U 0 u J t z U I IT C u J C J rl C I u U 0 w t z V V Ll t 1797 FLOPPY V DISK CONTROLLER v DATA SEPARATION AND WRITE PRECOMPEN SATION V1 H 207 BLOCK...

Page 43: ...ludes track density number of recording sides to the disk and if precompensation is being used The control latch accepts commands to the disk drives such as DRIVE SELECT 5 FASTEP and others that have...

Page 44: ...ough pins 35 36 38 39 40 88 89 and 90 on the bus interface plug This data is latched by tri state latch U35 The latch is used because data on the S 100 bus is not present long enough for the 1797 to r...

Page 45: ...a known state before the CPU accesses the board In the 1797 the reset line sets the command register at 03H the sector register to 01H and bit 7 of the status register Not Ready bit to logic zero Afte...

Page 46: ...to be read There are two sources of status information for the S 100 bus the status port at U31 and the 1797 status register in U22 To read from the status port the CPU selects the H 207 by placing th...

Page 47: ...TRQ o no interrupt interrupt request request from 1797 1 MOTORON 5 0 spindle motor 1 spindle motor not running running 3 96TPl o 5 25 drives 1 5 25 drives are 48 TPI are 96 TPl 4 PRECCl1P o 5 25 drive...

Page 48: ...select drive 4 2 8 5 0 sel ect 5 25 1 select 8 3 WEN 0 deBt hot 1111 1 Seleot drive drive peoified by bit O 1 and 2 4 PREC IP 5 25 DDEN 0 precomp all 1 disable precomp tracks 8 DDEN 0 precanp all 1 pr...

Page 49: ...e between F and E normal position for the H Z 100 At the completion of the access delay the wait state is cleared RDY is asserted and the CPU completes the read or wr i te of the data reg ister in the...

Page 50: ...ermines the next sector to be written to by making the AO and A1 signals equal to o and 1 A2 equal to O Software then writes the sector number to the sector register and the track number to the track...

Page 51: ...of Q4 which contains the DRQ signal delayed by three to four clock cycles is connected to jumper J1 post E For 6 MHz operation J1 is connected between post E and post F INTERRUPTS There are two interr...

Page 52: ...drive couples through U9 and U16 to U1 11 and U22 27 RAWREAD RDD contains both data bits and clock bits U1 extracts the clock bits and sends them to U22 26 as RCLK These pulses are synchronized with...

Page 53: ...ncy remains constant Pins 5 7 and 8 of u1 allow the 1797 to control clock separation and data recovery When pins 7 and 8 are low the data recovery circuits are enabled If pin 7 is high which happens d...

Page 54: ...setting U30 19 to logic one and sending it to the DDEN input at U1 15 The CPU also asserts the PRECOMP line at U30 12 This couples through U6 8 to TG43 at U1 9 TG43 must be high befure precompensatio...

Page 55: ...Plo All output signals to the drives are buffered through U8 and U10 except WG and HLD The WG signal is sent through transistor Q2 as described previously The HLD signal is inverted by U7 10 before b...

Page 56: ...ates U501A and U501B The result of the comparison is a pul se 40 nS wid e and 120 nS del ayed in reference to the write pul se If the write pulse has been adjusted for a 120 nS pulse width the write p...

Page 57: ...y enable Data in bits on the S 100 bus in with respect to the CPU not the Controller Direction of drive head When high the drive head is stepping in When low the drive head is stepping out Data out bi...

Page 58: ...begin PD Pump down Decreases the frequency of the raw read data tracking clock PRECOMP Enables precompensation when low PU Pump up Increases frequency of the raw read data tracking clock pWR Valid da...

Page 59: ...atory precompensation in double density 8 drive TK Track O The drive read write head is over track o on the diskette TWOSIOEO The 8 drive is set for two sided operation with a two sided diskette VFOE...

Page 60: ...t When this signal is received no write command can take place and write protect bit in the status register is set Precompensated wri te data pulses that have been reshaped by U16 5DS 5DS3 Five inch d...

Page 61: ...INTRODUCTION ALL IN ONE LOW PROFILE DISASSEMBLY 5 147 5 147 5 149...

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Page 63: ...crewdriver slide the latch bracket to the center of the slot in the cabinet top The latch bracket is spring loaded so you will have to work with one side of the cabinet top at a time While holding the...

Page 64: ...H 207 board Lift up on the H 207 board extractors to pop the board free from the S 100 bus connector Now lift the H 207 board from the card cage This completes the removal of the H 207 board from the...

Page 65: ...per fonn the procedure on the other side Be sure to hold the freed side up so it will not snap back down Jr G lC 1tI cabinet top and set it safe place Disconnect the 50 conductor cable at P1 and the...

Page 66: ...5 150 TECHNICIAN NOTES...

Page 67: ...VISUAL CHECKS DISK CONTROLLER BOARD CABLE CONNECTIONS AND SWITCH POSITIONS 5 153 COMPONENT VALUES AND LOCATIONS 5 154...

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Page 69: ...ER BOARD CABLE CONNECTIONS AND SWITCH POSITIONS IN AN H Z IOO ENVIRONMENT 811 DRIVE CABLE INTERNAL 5 1 411 DRIVE CABLE SWITCH SET FOR HEATH 48 TPI 5 1 411 DRIVES fl6 3210 O 0 BB ij PORT ADPRESSllt G N...

Page 70: ...4 411 0 22pF 2 757 C 33 I 25 93 UI Y r Y r Y 1 RP 1 i I 0 18 01 C9 nRU C25 elf _ 0 32 OS34 2 3 0 14 20 U9 20 I TC43 reO 443 1000 14 74l5 241 14lS240 7 5132 74 533 443 824 443 7 3 JO 1 U3 s 4 3 792 44...

Page 71: ...DATA SEPARATOR ADJUSTMENT 5 157 Frequency Counter Method 5 158 Kit Builder Method 5 159 WRITE PRECOMPENSATION ADJUSTMENTS 5 160 Calibration Circuit Board Method 5 160 Procedure 5 161 Oscilloscope Meth...

Page 72: ...5 156 cPt CP2 c P 3 J2 H 207 CONTROLLER BOARD CONTROLS AND JUMPER LOCATIONS os 10 82...

Page 73: ...pacitance Probe Multimeter Oscilloscope H 207 Calibration Board IM 2420 or equivalent optional PKW 105 or equivalent IM 2202 or equivalent 10 4510 or equivalent See H 207 assembly manual HE 595 2909 f...

Page 74: ...ad to the CP2 test point Adjust the BIAS control R2 until the multimeter display shows 1 40 VDC 05 volts Switch the multimeter to lower ranges to perform this adjustment accurately Disconnect the mult...

Page 75: ...2 until the multimeter display shows 1 40 VDC 05 volts You will want to switch the multimeter to lower ranges to perform this adjustment accurately Allow a period of 15 minutes for drifting then perfo...

Page 76: ...nS This is the value used for Heath Zenith 48 TPI 5 1 4 disk drives that are included in the H Z 100s The jumpers at JO and J2 remain at the stock position That is JO is out and J2 is in the 8 5 posit...

Page 77: ...rd If not already done set R3 fully counterclockwise and R4 fully clockwise Set the jumper select wire of the calibration board to 120 nS If the drive requires more precompensation set the jumper to t...

Page 78: ...Precomp 1 Double Density JO IN JO X JO OUT Precomp is bi t 4 in the control latch X Don t Care NOTE Precomp is automatically disabled in single density operation Set the PRECMP 2 control R4 to a full...

Page 79: ...routine on a 5 1 4 diskette While format is running adjust the PRECMP 2 control R4 until the pulse width displayed on the oscilloscope corresponds to the manufacturer s suggested write precompensation...

Page 80: ...ay a 100 to 300 nS negative going pulse Apply power to the computer While formatting a 5 1 4 diskette adjust the PRECMP 1 control R3 until the pulse width displayed on the oscilloscope corresponds wit...

Page 81: ...SHOOTING INTRODUCTION EQUIPMENT NEEDED H Z 100 TEST FIXTURE PREWORK SERVICE HINTS Voltage Checks Logic Level Checks H 207 DISK CONTROLLER TEST WAVEFORMS 5 167 5 167 5 167 5 168 5 169 5 169 5 170 5 171...

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Page 83: ...and corrected EQUIPMENT NEEDED Frequency Counter IM 2420 or equi val ent Logic Probe IT 471 0 or equival ent Low Capacitance Probe PKW 105 or equi val ent Multimeter IM 2260 or equivalent Oscilloscope...

Page 84: ...r 03 installed incorrectly D1 D2 or D3 installed backwards ICs installed backwards Dirty S 100 board contacts Solder bridges Cold solder joints Resistor packs installed backwards Correct jumpering Swi...

Page 85: ...oller board The voltage at PS 1 5 is 5 VDC The voltage at PS2 12 is 12 VDC The voltage at PS3 5 is 5 VDC The voltage at CP2 is 1 40 VDC t VDC 5VDC 1 40 VDC 12VDC FLa PY DISK PI CONTROl 1 R If the volt...

Page 86: ...o it You must do this because this checkout procedure gives only the most likely causes to the problem It doesn t cover such things as open ground foils shorted foil runs or open resistors As you make...

Page 87: ...U 31 15 H U32 6 H U35 11 p U36 1 H U36 19 H End of test IF NOT OKAY CHECK U21 8 U13 6 U7 5 Also press and release CTR RESET U7 4 should remain low for about 18 seconds If not then replace U15 U30 or t...

Page 88: ...3 L U10 17 H UlO 17 U33 9 U11 3 H U11 5 H U11 9 H U11 11 L U11 13 H U16 7 U24 14 U24 12 U24 15 U24 13 U12 3 U12 5 U12 9 U12 11 4 MHz 2 MHz 1 MHz 2 MHz U18 is bad U12 3 U12 11 U12 5 U4 9 U4 5 U13 4 U1...

Page 89: ...U21 2 H U27 8 U21 3 H U21 1 U21 2 U21 4 H U17 15 U21 5 P U33 12 U21 6 H U21 4 U21 5 U21 8 L U21 10 U21 1O L U22 of data bus is defective U21 11 H U21 12 U21 13 U21 12 H U27 11 U21 13 P U33 12 U22 39 L...

Page 90: ...L U10 3 U25 4 L U22 39 U25 5 L U19 14 U25 6 H U25 3 U25 4 U25 5 U25 12 H U25 1 U25 2 U25 13 U25 13 L U22 39 U26 2 H U23 6 U26 3 L U20 5 U26 4 H U25 12 U26 5 H U26 2 U26 3 U26 4 U26 8 L U26 10 U26 11...

Page 91: ...9 19 U28 12 H U28 1 U28 13 L U28 11 U28 12 U29 19 p U29 U34 or OSl defective U30 1 H U33 9 U30 11 H U21 6 U30 16 L U30 1 U30 11 or data bus problem U32 5 H U27 3 U33 9 H U33 defective U33 12 p U33 def...

Page 92: ...state the frequency of RCLK is around 250 kHz 2V DIV I _ _ t _ _ _ 2 uS D11J The waveform at the right was taken from U22 24 This is the CLK signal that originates from the oscillator circuits The fr...

Page 93: ...DISK CONTROLLER CIRCUIT BOARD CALIBRATION CIRCUIT BOARD PARTS LISTS 5 179 5 180...

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Page 95: ...HE 6 124 12 C19 22 pf ceram1c HE 21 757 C63 1 uf ceram1c HE 21 762 R19 237 ohm 1 4 watt 1S HE 6 2370 12 C20 22 pf cer8lll1c HE 21 757 R20 1 lIelohlll 1 4 watt 5S lIE 6 105 12 C21 22 pf ceram1c HE 21 7...

Page 96: ...right angle HE 432 1053 U15 96LS02 HE 443 1040 oonneotor U16 96LS02 HE 443 1040 PI 50 pin right angle HE 432 1197 U17 74LS 138 HE 443 877 oonneotor U18 4 000 MHz oao111ator HE 150 132 U19 74LS175 HE...

Page 97: ...CIRCUIT BOARD X RAY VIEW...

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