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Z3 Technology Z3-DM8169-4CH-RPS, User Manual

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Z3 Technology Z3-DM8169-4CH-RPS User Manual Download Page 57

 

    

CONFIDENTIAL

                          Z3-DM8169-4CH-RPS V2.01.30a 

 
 

___________________________________________________________________________________________ 

Z3 Technology, LLC 

♦

 100 N 8

th

 ST, STE 250 

♦

 Lincoln, NE 68508-1369 USA 

♦

 +1.402.323.0702 

57 

while(((RD_MEM_32(CM_DEFAULT_TPPSS_CLKSTCTRL) & 0x7F00)>>8)!=0x7F); 
while(((RD_MEM_32(CM_DEFAULT_TPPSS_CLKCTRL)&0x30000)>>16)!=0); 
Bring TPP out of Local Reset 
PRCM for TPPSS is Done Successfully 
insmod /opt/z3/tppss/ti_dmx_io_ctrl.ko 
IOCTRL Major : 250 
insmod /opt/z3/tppss/tppss_tso.ko 
TPPSS TSO Init - debug mode is disabled 
TPPSS TSO:: registered module successfully! 
initialize tso data structures 
create proc read entries... 
tso_core_thread:471> TPPS_CORE TSO Core Thread Started. 
tso_core_thread:479> TPPS_CORE TSO Thread running. 
tso_core_thread:471> TPPS_CORE TSO Core Thread Started. 
tso_core_thread:479> TPPS_CORE TSO Thread running. 
remove stale /dev/tppss_dmx 
major number for /dev/tppss_dmx = 251 
remove stale /dev/tppss_dmx_io 
major number for /dev/tppss_dmx_io = 250 
remove stale /dev/tppss_tso 
major number for /dev/tppss_tso = 234 
downrate the ts clock 
/dev/mem opened. 
Memory mapped at address 0x4024e000. 
Value at address 0x4818034C (0x4024e34c): 0x0 
Written 0x2; readback 0x2 
/sys/kernel/debug is not a mountpoint 
load fpga1 
Use FPGA slave parallel mode 
Design filename fpga_0001_01.ncd;HW_TIMEOUT=FALSE;UserID=0xFFFFFFFF 
Part num len=13 
Part number 6slx16csg324 
Date 2014/03/18 
Time 10:17:20 
Bitstream size 464752 
fpga_write: init_b low 
FPGA write failed 
Use FPGA slave parallel mode 
Design filename fpga_0001_01.ncd;HW_TIMEOUT=FALSE;UserID=0xFFFFFFFF 
Part num len=13 
Part number 6slx16csg324 
Date 2014/03/18 
Time 10:17:20 
Bitstream size 464752 
fpga_write: init_b low 
FPGA write failed 
Use FPGA slave parallel mode 
Design filename fpga_0001_01.ncd;HW_TIMEOUT=FALSE;UserID=0xFFFFFFFF 
Part num len=13 
Part number 6slx16csg324 
Date 2014/03/18 
Time 10:17:20 
Bitstream size 464752 
fpga_write: init_b low 
FPGA write failed 
Use FPGA slave parallel mode 

Summary of Contents for Z3-DM8169-4CH-RPS

Page 1: ...on 2 01 30a August 4 2014 Before attempting to connect or operate this product please read these instructions carefully and save the manual for future use This document contains proprietary and confidential information of Z3 Technology LLC Z3 This document may not be used reproduced disclosed or disseminated to anyone without the prior written approval of an authorized representative of Z3 ...

Page 2: ...x1080p60 support 4K2K support RC 2 00 21 03 28 14 Updated for version 2 00 21e RC 2 00 21a 03 29 14 Fixed a typo RC 2 01 30 08 04 14 Updated screenshots and filenames added Quick Start Guide in Section 2 updated Features in Section 3 updated Encoder Guide to focus on 4 RTP channels in Section 6 updated Section 7 removed unnecessary TFTP NFS setup commands in Section 8 added section on Updating the...

Page 3: ...and Running the Make Script 10 5 0 CODE OVERVIEW 12 5 1 The z3apps rdk directory 12 5 1 1 rdk_demo 12 5 1 2 z3_mcfw_api 13 5 1 3 z3 13 5 2 Z3 Application Overview 13 5 2 1 Application Names and Locations 13 5 2 2 Application Options and Arguments 13 5 2 3 Application Source Code 14 5 3 RDK documentation 15 6 0 USING THE Z3 8169 4CH RPS TO ENCODE 4 RTP STREAMS 17 6 1 Set up the Video Sources 17 6 2...

Page 4: ...1 Updating the Image File 37 8 2 Method 2 Running Your Code through TFTP NFS 38 8 3 Other available u boot commands 41 9 0 USING THE PASSWORD FEATURE 43 10 0 SUMMARY OF OPTIONS 45 10 1 The System Setup Tab 45 10 2 The User Presets Tab 45 10 3 The Status Tab 46 10 4 The MTS Tab 47 10 5 The CH1 Tab 47 10 6 The CH2 CH4 Tab 50 10 7 Values Appearing at the Bottom of All Tabs 50 Appendix A BOOT LOG 51 A...

Page 5: ...e 26 Figure 13 VLC File Open Screen 27 Figure 14 Example of Z3 Video Streaming to VLC RTP 27 Figure 15 Viewing Bitrate in VLC 29 Figure 16 Changing the Bitrate Dynamically 30 Figure 17 Drop in Bitrate after Dynamic Bitrate Change 31 Figure 18 Tuning for Various Use Cases 32 Figure 19 The User Presets Tab 33 Figure 20 Entering a User Preset Name 33 Figure 21 Setting z3_test as the preset configurat...

Page 6: ...t up to four channels of 1080i It includes the interface used to connect the serial port The Z3 DM8169 MOD 3X features a unique expansion interface comprised of five high density connectors providing access to most of the interface signals available from the DM8169 processor Figure 1 below shows the Z3 DM8169 MOD 3X System on Module 86 mm An application board the Z3 DM8168 APP 5X is available from...

Page 7: ...nfigured There is no need to port or integrate OS functions media functions etc The software bundle also contains tools to allow the development of high level applications using hardware accelerated video processing DSP and graphics Those customers that license the optional source code package can also receive source code for Z3 s demonstration applications providing an ideal starting point for cu...

Page 8: ...RPS It also describes how to dynamically change the bitrate and how to store configurations set DHCP 2 2 If you already have a system from Z3 and need to update the firmware You can update the firmware via the web GUI interface by following the instructions in Section 8 0 RUNNING THE CODE YOU BUILT ON THE BOARD on page 37 2 3 If you are ready to start development Details on how to untar and build ...

Page 9: ...g On the fly bit rate changes Inputs 3G SDI Outputs 3G SDI DVB ASI Additional Interfaces include 2xSATA2 USB 2 0 2 USB 2 0 Interfaces for local storage Web based configuration software for user friendly configuration and control RS232 serial port for technical configuration and control An optional upgrade for 4K30 2160p30 support is available Please contact sales z3technology com for pricing of 4K...

Page 10: ...essary to install some 32 bit libraries for the cross compiling toolchain You can determine whether your OS is 64 bit by using the uname p command A 64 bit OS will return x86_64 while a 32 bit OS will return i386 i586 or i686 For 64 bit Ubuntu you can get the necessary libraries by typing sudo apt get install ia32 libs For 64 bit Fedora you can type sudo yum install glibc i686 4 2 Making the Direc...

Page 11: ...an take around 30 40 minutes You will also need to type in the sudo password a few times towards the end of the build The outcome of the build process should be newly created image files in the images directory You can confirm this by doing the following cd images ls alt The result should be something like the following Note that actual filenames dates and times will differ Figure 3 Sample Content...

Page 12: ...3 DM8169 4CH RPS is run from the run sh script in dvr rdk dvr_rdk bin ti816x This code calls the z3_dvr_rdk_demo_mcfw_api out binary which initializes and runs the encoder This binary is built from the dvr rdk directory The code for the binary resides in z3apps rdk rdk_demo The z3apps rdk directory is described in more detail in the next section 5 1 The z3apps rdk directory There are 3 main subdir...

Page 13: ...e first is a menu based demo this is what comes up in the serial terminal when the board is powered on The second is a command line interface that is more flexible and easier to use from a programming standpoint The web based interface uses the command line interface extensively The menu based demo binary can be found at opt dvr_rdk ti816x bin z3_dvr_rdk_demo_mcfw_api out The command line interfac...

Page 14: ...to encode For example encode instance 1 source HDMI1 dst rtp 192 168 0 6 5004 audio off will start an encode from HDMI1 streaming to 192 168 0 6 at port 5004 You can find an example of using this in a script at PRJROOT dvr rdk runz3demo sh 5 2 3 Application Source Code The application source code can be found mainly in z3apps rdk rdk_demo The top level file for the menu driven demo is demo c The t...

Page 15: ...M81xx_DVR_RDK_Audio_Notes pdf DM81xx_DVR_RDK_AVSync_Notes pdf DM81xx_DVR_RDK_Boot_Logo_and_External_Device pdf DM81xx_DVR_RDK_Customer_Display_Resolution pdf DM81xx_DVR_RDK_Debug_Statistics pdf DM81xx_DVR_RDK_Display_Output_Configuration pdf DM81xx_DVR_RDK_Ethernet_Offload_Driver pdf DM81xx_DVR_RDK_External_Video_Device_Configuration pdf DM81xx_DVR_RDK_Flash_File_FS pdf DM81xx_DVR_RDK_Graphics_Usi...

Page 16: ...de_Display pdf DM814x_DVR_RDK_UseCaseGuide_4D1_8CIF_16CIF_DVR pdf DM814x_DVR_RDK_UseCaseGuide_Decode_Display pdf DM816x_DVR_RDK_UseCaseGuide_16D1_DVR pdf DM816x_DVR_RDK_UseCaseGuide_32D1_Decode_Display pdf DM816x_DVR_RDK_UseCaseGuide_SD_HD_Encode_Card pdf DM81xx_DVR_RDK_Interlace_UseCaseGuide pdf UserGuides DM8168_DVR_RDK_GUI_Guide pdf DM816x_FAPLL xls DM81xx_DVR_RDK_Demo_Guide pdf DM81xx_DVR_RDK_...

Page 17: ...inputs is not currently supported in the Z3 DM8169 4CH RPS The Z3 DM8169 4CH RPS will encode at the same resolution that the video is being input Each of the channels can be different resolutions For example it is possible to combine 1 1080i 1 720p 1 D1 and 1 CIF or any combination of the above simultaneously 6 2 Connect the Z3 DM8169 4CH RPS For these steps please refer to Figure 4 2 Connect the ...

Page 18: ...After about 1 to 2 minutes you will see the RPS Main Menu shown on next page Note the local IP address and netmask typically 192 168 81 68 and 255 255 0 0 This is the IP address of the board You will need this later to access the web interface 6 5 Ensure your PC has a proper IP address 8 To be able to communicate with the board the PC that you are communicating from needs to have the same first 2 ...

Page 19: ...S V2 01 30a ___________________________________________________________________________________________ Z3 Technology LLC 100 N 8th ST STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 19 Figure 5 Z3 DM8169 4CH RPS Serial Main Menu ...

Page 20: ...ts Z3 recommends FireFox or Chrome In this browser type the IP address of the board noted in step 7 for example if the default value is used it would be http 192 168 81 68 After about 3 seconds the control menu should come up 10 Click on the CH1 tab 11 You should see the Channel 1 configuration tab In this tab set Output Format to RTP and Dest Address to the IP address of your PC in this example 1...

Page 21: ...___________________________________________________________ Z3 Technology LLC 100 N 8th ST STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 21 Figure 7 Z3 DM8169 4CH RPS CH1 Settings a Change format to RTP b Change Dest Address to PC IP address c Make sure Dest Port is 5004 ...

Page 22: ...Z3 Technology LLC 100 N 8th ST STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 22 6 7 Configure CH2 CH4 12 Do the same for CH2 to CH4 The port settings for CH2 CH4 should be 5006 5008 and 5010 respectively After you are finished the settings should be the same as shown in Figure 8 to Figure 10 Figure 8 Z3 DM8169 4CH RPS CH2 Settings ...

Page 23: ...RPS V2 01 30a ___________________________________________________________________________________________ Z3 Technology LLC 100 N 8th ST STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 23 Figure 9 Z3 DM8169 4CH RPS CH3 Settings ...

Page 24: ...RPS V2 01 30a ___________________________________________________________________________________________ Z3 Technology LLC 100 N 8th ST STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 24 Figure 10 Z3 DM8169 4CH RPS CH4 Settings ...

Page 25: ...above If the encoders are running you should first click Stop All wait for status to say STOPPED and then click Start All for the new settings to take effect 14 Click on the Status tab just to the right of User Presets You should see output bitrates frame rates and resolutions for each channel This is shown on the next page Important Note When encoding first starts it may take around 1 minute for ...

Page 26: ... 4CH RPS V2 01 30a ___________________________________________________________________________________________ Z3 Technology LLC 100 N 8th ST STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 26 Figure 12 Example Status Page ...

Page 27: ...T STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 27 6 9 Run VLC to View Stream 1 15 Run VLC on your PC version used in testing at Z3 2 05 16 Select Media Open File Select the file z3 netra sdp included with this release 16 Press Enter 17 You should now see video streaming to VLC Figure 13 VLC File Open Screen Figure 14 Example of Z3 Video Streaming to VLC RTP ...

Page 28: ...sible that the PC may not be powerful enough to view all 4 channels at the same time It has been observed on some slower PCs that 3 channels can be viewed and then when the 4th one is attempted all 4 channels stop displaying If this is observed this is a PC VLC issue and not a Z3 DM8169 4CH RPS issue Important Note The important parts of the SDP files are the port numbers used for video and audio ...

Page 29: ... Changing the bitrate dynamically The Z3 DM8169 4CH RPS includes an update button which allows you to change the bitrate without stopping and restarting the encoder To use it do the following steps 24 In VLC click on Tools and select Codec Information This brings up a window with 4 tabs Select the Statistics tab In this tab you can see the current video audio bitrate Figure 15 Viewing Bitrate in V...

Page 30: ..._______________________________________ Z3 Technology LLC 100 N 8th ST STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 30 25 In the CH1 screen change the bitrate from 6000K to 2000K and click the update button Figure 16 Changing the Bitrate Dynamically 2 Click update 1 Change bitrate to 2000K ...

Page 31: ...________________________________ Z3 Technology LLC 100 N 8th ST STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 31 26 You should see the quality of the picture in VLC change You should also observe the video bitrate drop Figure 17 Drop in Bitrate after Dynamic Bitrate Change Lower video audio bitrate ...

Page 32: ... for challenging content However a higher value also causes latency to increase accordingly To minimize latency this value should be set to the lowest possible value The lowest value Z3 recommends is 100 B frames improve the quality of the picture but they also increase the latency by 1 frame time To minimize latency B frames should be disabled done by setting Number of B frames to 0 Figure 18 sho...

Page 33: ... is set up a custom configuration and save this so that the DHCP setting is used the next time the system boots up To do this click on the User Presets tab and click on new 28 This brings up a new text box to enter the preset name Type z3_test and click ok 29 Now go back to the System Setup tab Go to the bottom of the screen and select the z3_test preset that you just created The system might take...

Page 34: ... NE 68508 1369 USA 1 402 323 0702 34 30 Click on the Use DHCP checkbox and then click Save just under z3_test 31 When you do this a window pops up reminding the user that for changes to IP Address Local Netmask Default Gateway to take effect a reboot is required Click Ok Figure 22 Setting DHCP Figure 23 Reboot Reminder for Changing IP Settings 1 Click on Use DHCP 2 Click on Save ...

Page 35: ...al interface you established in steps 5 and 6 When the Main Menu comes up you should see the IP address that was dynamically assigned 34 Finally type that address into a web browser When the GUI comes up you have confirmed the reassignment through DHCP 39 You can go back to Static IP by unchecking Use DHCP and saving that to the preset One note the value of Local IP Address specifies the IP addres...

Page 36: ...ptions in the GUI to exercise other features Section 10 0 SUMMARY OF OPTIONS lists the different items that can be changed in detail Besides using the web based GUI you can also use the serial menus More detailed system information can also be gained from the options in the serial interface A command line interface called MCSENC is also available for running commands This can be invoked with the c...

Page 37: ... to your development PC 8 1 Method 1 Updating the Image File 1 Run the Web Interface Steps 1 9 in Section 6 0 2 Select update device firmware from the main screen 3 This brings you to the Software Updater screen Click Browse and browse to the directory z3 netra rdk z3 netra DM8169 4CH RPS date images and select the image file z3 netra upd img 4 Click Open 5 Click Upload and Update You should see a...

Page 38: ...e tftp disable no socket_type dgram protocol udp wait yes user nobody server usr sbin in tftpd server_args s home c Start TFTP sudo etc init d xinetd start 2 Enable NFS on the Linux PC The target DM8169 will mount the root file system using NFS This like TFTP will also vary depending on the Linux setup you have As an example here is a set of steps that would be run from Ubuntu 10 x or later these ...

Page 39: ...variable script to match your own environment settings Go to the u boot directory in the release directory and edit the file u boot env netra rdk txt here emacs is used any text editor can be used cd home z3 z3 netra rdk cd z3 netra RDK 20140728 cd u boot emacs u boot env netra rdk txt d In the editor you want to modify the values for nfsserver serverip gatewayip netmask ipaddr tftp_root and nfs_r...

Page 40: ...ettings window From here set Newline tx delay ms option D to 100 and Character tx delay ms option F to 1 g Press return to save your terminal settings h The next step is to read in the u boot environment file you just modified If you are using minicom type ctl A and Z to bring up the Command Summary Then type Y for Paste file i This should bring up the Select file for upload window pointing to you...

Page 41: ... u boot prompt type boot Z3 DM8168 MOD boot You should see the DM8169 4CH RPS boot the kernel obtained via TFTP mount a file system using NFS and then go straight to the serial menu If you are running into issues see the Troubleshooting section in Appendix B 8 3 Other available u boot commands Besides booting from NAND and TFTP NFS there are other boot configurations that are possible Below are th...

Page 42: ...323 0702 42 The following scripts are also available to update the u boot environment run update uboot Update u boot bootloader in NAND run update kernel Update Linux kernel image run update env Update u boot environment settings run update ramdisk Update root filesystem ramdisk run update jffs2 Update jffs2 image requires mtd utils on host run update ubifs Update jffs2 image requires ubi utils on...

Page 43: ...ORD FEATURE The Z3 DM8169 4CH RPS includes an optional password to prevent unauthorized users from accessing the Web GUI The steps for using it are shown below 1 In the System Setup tab click on go next to Set Password 2 Once you click on go the change password options appear Enter the new password twice and click change Figure 31 Selecting Set Password Figure 32 Changing the Password Click here E...

Page 44: ...68508 1369 USA 1 402 323 0702 44 3 Wait for the password options to disappear This indicates that the password has changed 4 Retype the IP address in the web browser You should then see a prompt for a user name and password Use admin for the user name and the value you had entered before for the password 5 You should now be able to access the web GUI Figure 33 Password Entry Screen ...

Page 45: ...Netmask 255 255 z w 255 255 0 0 Sets the netmask of the Z3 DM8169 4CH RPS Default Gateway 192 168 a b 192 168 0 1 Can generally leave this as 192 168 0 1 Use DHCP Checked Unchecked See the section on DHCP configuration Set Device Name Can use to set name for Z3 DM8169 4CH RPS Set Password Can use to assign a password update device firmware See Making a Firmware Update on p 37 10 2 The User Presets...

Page 46: ...ed every 2 seconds Width Width of encoded picture Height Height of encoded picture If interlaced encoding is occurring the height of each field is output for example 1080i encode would have a value of 540 for height Audio Status Channel The channel number 1 4 Subchannel Always 1 in this release Codec The codec being used to encode audio for that channel Stream Status Channel The channel number 1 4...

Page 47: ...ample an input frame rate of 30fps with a divider of 2 would cause an output stream of 15fps Number of B frames 0 2 2 The number of B frames A value of 0 means B frames are disabled GDR Refresh Rate 0 240 GDR stands for Gradual Decoder Refresh When set to 0 GDR is disabled When set to a nonzero value it determines the intra refresh rate If GDR is set to 30 for example then each frame will have a s...

Page 48: ...122 123 If UDP format is selected the PID to use for that audio channel RTP Port 0 9999 8892 8898 If RTP format is selected the port associated with that audio channel Max PTS PCR 0 9999 250 Allows user to specify a smaller interval than 250ms between PTS and PCR This is for specialized applications It is generally recommended to leave this value at 250 Output Format RTP UDP TSFILE FILE MPTS Outpu...

Page 49: ...Only 0 999 520 PID assigned to PCR in the TS stream PMT PID UDP Only 0 999 164 PID assigned to PMT in the TS stream TS Rate UDP Only 125K 20000K 8000K The rate of the transport stream Normally this value should be set to 1 25 video bit rate audio bit rate This can be set to higher values to allow leeway for times when many bits are needed to encode This can be especially useful for ensuring smooth...

Page 50: ... 8914 8916 8922 Video RTP Port 5004 5006 5008 5010 Video PID 301 302 303 304 PCR PID 501 502 503 504 PMT PID 161 162 163 164 10 7 Values Appearing at the Bottom of All Tabs Parameter Options default in bold Notes preset serial_menu encoder factory default any user defined profiles The configuration file to use serial_menu Last value saved in GUI encoder factory default Factory settings Can also ad...

Page 51: ...om Legacy Image at 81800000 Image Name Linux 2 6 37 Image Type ARM Linux Kernel Image uncompressed Data Size 2452228 Bytes 2 3 MiB Load Address 80008000 Entry Point 80008000 Verifying Checksum OK Loading Kernel Image OK OK Starting kernel Uncompressing Linux done booting the kernel Linux version 2 6 37 neal ubuntu01 gcc version 4 5 3 20110311 prerelease G CC 1 Mon Jul 28 15 58 13 CDT 2014 CPU ARMv...

Page 52: ... data 0xc04ac000 0xc04f0840 275 kB SLUB Genslabs 11 HWalign 64 Order 0 3 MinObjects 0 CPUs 1 Nodes 1 NR_IRQS 375 IRQ Found an INTC at 0xfa200000 revision 5 0 with 128 interrupts Total of 128 interrupts on 1 active controller GPMC revision 6 0 Trying to install interrupt handler for IRQ368 Trying to install interrupt handler for IRQ369 Trying to install interrupt handler for IRQ370 Trying to instal...

Page 53: ...ocksource gp timer musb hdrc version 6 0 host debug 0 musb hdrc musb hdrc 0 dma type dma cppi41 MUSB controller 0 revision 4ea20800 musb hdrc musb hdrc 0 MUSB HDRC host driver musb hdrc musb hdrc 0 new USB bus registered assigned bus number 1 usb usb1 New USB device found idVendor 1d6b idProduct 0002 usb usb1 New USB device strings Mfr 3 Product 2 SerialNumber 1 usb usb1 Product MUSB HDRC host dri...

Page 54: ...yO2 at MMIO 0x48024000 irq 74 is a OMAP UART2 console ttyO2 enabled bootconsole disabled console ttyO2 enabled bootconsole disabled brd module loaded loop module loaded ahci probe devid name is ahci ahci CAP register dump 0x6726ff81 Modified ahci CAP register dump 0x6f26ff81 ahci ahci 0 forcing PORTS_IMPL to 0x3 ahci SSS flag set parallel bus scan disabled ahci ahci 0 AHCI 0001 0100 32 slots 2 por...

Page 55: ...0 driver unknown davinci_mdio davinci_mdio 0 phy 1 device 0 01 driver unknown usbcore registered new interface driver cdc_ether usbcore registered new interface driver dm9601 Initializing USB Mass Storage driver usbcore registered new interface driver usb storage USB Mass Storage support registered mice PS 2 mouse device common for all mice omap_rtc omap_rtc rtc core registered omap_rtc as rtc0 i2...

Page 56: ...fs UBIFS file system size 195289088 bytes 190712 KiB 186 MiB 1538 LEBs UBIFS journal size 9023488 bytes 8812 KiB 8 MiB 72 LEBs UBIFS media format w4 r0 latest is w4 r0 UBIFS default compressor lzo UBIFS reserved for root 0 bytes 0 KiB VFS Mounted root ubifs filesystem on device 0 14 devtmpfs mounted Freeing init memory 220K init started BusyBox v1 15 0 svn 2014 07 28 16 00 51 CDT starting pid 49 t...

Page 57: ...r for dev tppss_dmx 251 remove stale dev tppss_dmx_io major number for dev tppss_dmx_io 250 remove stale dev tppss_tso major number for dev tppss_tso 234 downrate the ts clock dev mem opened Memory mapped at address 0x4024e000 Value at address 0x4818034C 0x4024e34c 0x0 Written 0x2 readback 0x2 sys kernel debug is not a mountpoint load fpga1 Use FPGA slave parallel mode Design filename fpga_0001_01...

Page 58: ...1484404 Wrote 1484404 bytes Check done VID DONE 0x0001 AUD DONE 0x0001 load the lcd BoardID 256 Configure 30 0005 board 0x00A5 0x00AD adv7611 1 004c chip found 0x98 OMAP I2C adapter adv7611 1 004c Write retry 3 adv7611 1 004c Write retry 2 adv7611 1 004c Write retry 1 i2c i2c 1 adv7611 i2c write failed addr 4c reg x01 value x06 adv7611 1 004c Write retry 3 adv7611 1 004c Write retry 2 adv7611 1 00...

Page 59: ...ined Playback channels Mono Mono Playback on Simple mixer control Right PGA Mixer Mic3R 0 Capabilities pswitch pswitch joined Playback channels Mono Mono Playback on numid 1 iface MIXER name PCM Playback Volume type INTEGER access rw R values 2 min 0 max 127 step 0 values 127 127 dBscale min 63 50dB step 0 50dB mute 0 numid 22 iface MIXER name Line DAC Playback Volume type INTEGER access rw R valu...

Page 60: ...dsp Remote Debug Shared Memory 0xbf000000 m3video Remote Debug Shared Memory 0xbf010820 m3vpss Remote Debug Shared Memory 0xbf021040 m3video Received character s c6xdsp Remote Debug Shared Memory 0xbf000000 m3video Remote Debug Shared Memory 0xbf010820 m3vpss Remote Debug Shared Memory 0xbf021040 c6xdsp Received character s opt dvr_rdk ti816x dev mem opened Memory mapped at address 0x4025d000 Valu...

Page 61: ...eway 192 168 0 1 Change device name MVE 40 Change device password BLANK M Change mode enc_int_prog C Config Multi Program TS name sam enabled n Preset serial_menu 1 Change channel 1 H 264 RES 1920x1080 URL rtp 192 168 0 6 5004 VSRC HD SDI1 2 Change channel 2 H 264 RES 1920x1080 URL rtp 192 168 0 6 5006 VSRC HD SDI2 3 Change channel 3 H 264 RES 1920x1080 URL rtp 192 168 0 6 5008 VSRC HD SDI3 4 Chan...

Page 62: ... pinging the Z3 DM8169 4CH RPS IP address from the Linux PC Try pinging the Linux PC from the Z3 DM8169 4CH RPS Problem Do not see video in VLC Does the IP address set in Dest Address equal the IP address of the PC running VLC Does the port number in Dest Port equal the value entered in the URL for VLC Does the video coming out of the source match the resolution in the encoder settings Is the PC f...

Page 63: ...oes not come up Is the link to filesys properly set up see step 2c Does the IP address in the line added in etc exports match the IP address set in nfsserver in u boot Does the value of nfs_root in u boot point to z3 netra rdk filesys fs Did you start the NFS server If you modified the exports file did you remember to restart the NFS server after that When contacting Z3 Support for additional supp...

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