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User’s Manual

PPENDIX

D. A

LTERNATE

THE

ROGRAMMING

ORT

Appendix D provides additional information for the program-
ming port in association with the

DIAG

and

PROG

connectors

on the programming cable. The

PROG

connector is used only

when the programming cable is attached to the programming
connector (header J3) while a new application is being devel-
oped. Otherwise, the

DIAG

connector on the programming cable

allows the programming cable to be used as an RS-232 to
CMOS level converter for serial communication, which is
appropriate for monitoring or debugging a Jackrabbit system
while it is running.

Summary of Contents for BL1800

Page 1: ...Jackrabbit BL1800 C Programmable Single Board Computer User s Manual 019 00067 030131 E ...

Page 2: ...om Jackrabbit BL1800 User s Manual Part Number 019 0067 030131 E Printed in U S A 2000 2003 Z World Inc All rights reserved Z World reserves the right to make changes and improvements to its products without providing notice Trademarks Rabbit 2000 is a trademark of Rabbit Semiconductor Dynamic C is a registered trademark of Z World Inc ...

Page 3: ...irectional I O 12 2 3 A D Converter 13 2 4 D A Converters 15 2 4 1 DA1 16 2 4 2 DA0 18 2 5 Serial Communication 20 2 5 1 RS 232 20 2 5 2 RS 485 20 2 5 3 Programming Port 22 2 6 Memory 23 2 6 1 SRAM 23 2 6 2 Flash EPROM 23 2 7 Other Hardware 24 2 7 1 External Interrupts 24 2 7 2 Clock Doubler 24 2 7 3 Spectrum Spreader 25 Appendix A Specifications 27 A 1 Electrical and Mechanical Specifications 28 ...

Page 4: ...lies 45 C 2 Batteries and External Battery Connections 48 C 2 1 Battery Backup Circuit 49 C 2 2 Power to VRAM Switch 50 C 2 3 Reset Generator 50 C 3 Chip Select Circuit 51 Appendix D Alternate Use of the Programming Port 53 Notice to Users 55 Index 57 Schematics 59 ...

Page 5: ... 24 CMOS compatible I O 3 analog channels 1 A D input 2 PWM D A outputs 4 high power outputs factory configured as 3 sinking and 1 sourcing 4 serial ports 2 RS 232 or 1 RS 232 with RTS CTS 1 RS 485 and 1 CMOS compati ble 6 timers five 8 bit timers and one 10 bit timer 128K SRAM 256K flash EPROM Real time clock Watchdog supervisor Voltage regulator Backup battery Appendix A provides detailed specif...

Page 6: ...design an embedded microprocessor based system rapidly and effi ciently See the Jackrabbit BL1800 Getting Started Manual for complete information on the Development Kit Table 1 Jackrabbit Series Features Model Features BL1800 Full featured controller with switching voltage regulator BL1810 BL1800 with 14 7 MHz clock 128K flash EPROM linear voltage regulator sinking outputs sink up to 200 mA sourci...

Page 7: ...itial evaluation and development begin with at least a read through of the Getting Started manual In addition to the product specific information contained in the Jackrabbit BL1800 Get ting Started Manual and the Jackrabbit BL1800 User s Manual this manual several higher level reference manuals are provided in HTML and PDF form on the accompany ing CD ROM Advanced users will find these references ...

Page 8: ... EN61000 4 3 Radiated Immunity EN61000 4 4 EFT EN61000 4 6 Conducted Immunity Additional shielding or filtering may be required for a heavy industrial environment Emissions The Jackrabbit series of single board computers meets the following emission standards with the Rabbit 2000 spectrum spreader turned on and set to the normal mode The spectrum spreader is only available with Rev C or higher of ...

Page 9: ...recommends placing digital I O or analog cables that are 3 m or longer in a metal conduit to assist in maintaining CE compliance and to conform to good cable design practices Z World also recommends using properly shielded I O cables in noisy electromagnetic environments When installing or servicing the Jackrabbit it is the responsibility of the end user to use proper ESD precautions to prevent ES...

Page 10: ...6 Jackrabbit BL1800 ...

Page 11: ...uts A D Converter D A Converters Serial Communication Memory Figure 1 shows these Rabbit based subsystems designed into the Jackrabbit Figure 1 Jackrabbit Subsystems SRAM Flash 15 MHz osc 32 kHz osc BL1800 RABBIT 2000 RS 232 RS 485 Digital Outputs High Power Outputs Programming Port Digital Inputs A D Converter Analog Outputs ...

Page 12: ...dels are equipped with two 2 20 IDC headers J4 and J5 with a 2 mm pitch GND RXC TXC PC1 PC3 PC5 PC7 AGND DA1 PD1 PD3 PD5 PD7 GND 485 VCC SM1 STAT VBAT GND VCC RXB TXB PC0 PC2 PC4 PC6 AD0 DA0 PD0 PD2 PD4 PD6 GND 485 VCC SM0 IOBEN GND RST J5 GND PA0 PA2 PA4 PA6 GND PB0 PB2 PB4 PB6 WDO GND PE6 PE4 PE2 PE0 HV0 HV2 K GND VCC PA1 PA3 PA5 PA7 GND PB1 PB3 PB5 PB7 PCLK PE7 PE5 PE3 PE1 GND HV1 HV3 RAW VCC J...

Page 13: ... one additional CMOS level digital input PC1 Figure 3 Digital Inputs The actual switching threshold is approximately 2 40 V Anything below this value is a logic 0 and anything above is a logic 1 NOTE Since the voltage limits on the inputs to the Rabbit 2000 microprocessor are 0 to 5 5 V DC the end user must ensure that the voltage applied to any I O pin is within these limits 47 kW Rabbit 2000 Mic...

Page 14: ... supply for the four high power outputs is called K and is available on header J4 Connect K to the power supply that powers the load which is usually a separate power supply to that used for the Jackrabbit and must be no more than 30 V because of the power limitations of the resistors used in the sourcing output circuit The K connection performs two functions 1 K supplies power to the sinking sour...

Page 15: ...n in Figure 5 are turned on The maximum sourcing cur rent is 100 mA BL1810 and BL1820 or 500 mA BL1800 and the maximum K is 30 V This voltage limit on K arises because R51 and R52 at the base of Q28 can each dissipate 500 mW for a total of 1 W The 30 V limit then constrains the sinking outputs as well because K is common to all four high current outputs HV3 PE3 D24 C28 100 nF MMBT3906 Q28 R52 1 8 ...

Page 16: ... Bidirectional I O The Jackrabbit has 14 CMOS level bidirectional I O PA0 PA7 PD0 PD3 PD6 PD7 and PE4 PE5 The BL1820 which does not have RS 485 has one additional bidirectional I O PD5 J5 GND PA0 PA2 PA4 PA6 GND PB0 PB2 PB4 PB6 WDO GND PE6 PE4 PE2 PE0 HV0 HV2 K GND VCC PA1 PA3 PA5 PA7 GND PB1 PB3 PB5 PB7 PCLK PE7 PE5 PE3 PE1 GND HV1 HV3 RAW VCC GND RXC TXC PC1 PC3 PC5 PC7 AGND DA1 PD1 PD3 PD5 PD7 ...

Page 17: ...voltage is too high indicator If DA0 is larger than the analog voltage presented at AD0 then PE6 will be true high If this happens the pro gram will need to reduce the DA0 voltage PE7 can be imagined to be a DA0 voltage is too low indicator If DA0 is smaller than the analog voltage presented at AD0 then PE7 will be true high If this happens the pro gram will need to raise the DA0 voltage The A D i...

Page 18: ...elative accuracy between mea surements but no absolute accuracy This is because Vcc can vary 5 the pulse width modulated outputs might not reach the full 0 V and 5 V rails out of the Rabbit 2000 micro processor and the gain resistors used in the circuit have a 1 tolerance For these reasons each Jackrabbit needs to be calibrated individually with the constants held in software to be able to rely on...

Page 19: ...used Pulse width modulation PWM is used for the D A conversion This means that the digi tal signal which is either 0 V or 5 V is a train of pulses This means that if the signal is taken to be usually at 0 V or ground there will be 5 V pulses The voltage will be 0 V for a given time then jump to 5 V for a given time then back to ground for a given time then back to 5 V and so on A hardware filter i...

Page 20: ...the output voltage The maximum signal decay between pulses will occur when DA1 is set to 2 5 V This means the pulse train will have a 50 duty cycle The maximum signal decay will be where RC 0 01 s for 14 7 MHz Jackrabbits and t is the pulse on or off time not the length of the total cycle Timer B is driven at the Rabbit 2000 frequency divided by 2 The frequency achievable with a 14 7 MHz clock is ...

Page 21: ...be within 99 326 or within about 21 mV for a 3 V change in voltage after five time constants or 50 ms Six time constants 60 ms will allow settling to within 99 75 or to within about 8 mV for a 3 V change in voltage Seven time constants 70 ms will allow settling to within 99 91 or to within about 3 mV for a 3 V change in voltage An LM324 op amp which can comfortably source 10 mA throughout the D A ...

Page 22: ... remember that the DA0 output voltage will not be realized instantaneously after programming in a value There is a settling time because of the RC time constant R21 R27 C20 which is 7 68 ms For example the voltage at any given time is V VP VP VDA0 e t RC EQ 2 where V is the voltage at time t VP is the programmed voltage VDA0 is the last DA0 out put voltage from the D A converter and RC is the time...

Page 23: ...mA Below 1 V the D A converter can only sink a maxi mum of 100 µA The peak to peak ripple on DA0 is less than 3 mV There is a way to get rid of the ripple for very small periods of time To do that simply program the PWM port from a PWM output to a high impedance input This will allow the capacitor to hold the voltage subject only to leakage currents which add up to about 1 µA This will cause the c...

Page 24: ...C transmit and RXC serial port C receive on header J5 The maximum baud rate for each RS 232 serial channel is 115 200 bps RS 232 can be used effectively at this baud rate for distances up to 15 m Because two RS 232 transmit and two RS 232 receive lines are available one serial chan nel can be used for serial transmit and receive and the other serial channel can be used as a general digital I O for...

Page 25: ... PE4 PE2 PE0 HV0 HV2 K GND VCC PA1 PA3 PA5 PA7 GND PB1 PB3 PB5 PB7 PCLK PE7 PE5 PE3 PE1 GND HV1 HV3 RAW VCC GND RXC TXC PC1 PC3 PC5 PC7 AGND DA1 PD1 PD3 PD5 PD7 GND 485 VCC SM1 STAT VBAT GND VCC RXB TXB PC0 PC2 PC4 PC6 AD0 DA0 PD0 PD2 PD4 PD6 GND 485 VCC SM0 IOBEN GND RST J5 U6 U5 U3 J4 U1 J1 J2 J3 Y3 Rabbit 2000 SRAM RS 232 RS 485 U4 VIN GND GND RESET JACKRABBIT Z World Inc GND PA0 PA2 PA4 PA6 GN...

Page 26: ...e Jackrabbit to start up in an external bootstrap mode The programming port is used to start the Jackrabbit in a mode where the Jackrabbit will download a program from the port and then execute the program The programming port transmits information to and from a PC while a program is being debugged The Jackrabbit can be reset from the programming port The Rabbit 2000 status pin is also presented t...

Page 27: ... necessary to change the sector size in the future A Flash Memory Bank Select jumper configuration option exists at JP3 with 0 Ω surface mounted resistors for Jackrabbit boards labeled 175 0255 This option used in conjunc tion with some configuration macros allows Dynamic C to compile two different co resi dent programs for the upper and lower halves of the 256K flash in such a way that both progr...

Page 28: ...automatically in the BIOS for crystals or resonators with a frequency above 12 9 MHz The clock doubler may be disabled if 14 7 MHz clock speeds are not required Disabling the Rabbit 2000 microprocessor s internal clock doubler will reduce power consumption and further reduce radiated emissions The clock doubler is disabled with a simple change to the BIOS as described below 1 Open the BIOS source ...

Page 29: ...trong spreading NOTE The spectrum spreader is off by default for Jackrabbit BL1800 models and needs to be enabled for them to be CE compliant To allow the flash memory and RAM chips to accomodate the occasional higher frequencies associated with the spectrum spreader being turned on for the Jackrabbit BL1800 models only you will need at least one wait state for both the flash memory and the RAM Th...

Page 30: ...26 Jackrabbit BL1800 ...

Page 31: ...User s Manual 27 APPENDIX A SPECIFICATIONS Appendix A provides the specifications for the Jackrabbit ...

Page 32: ...ns for the Jackrabbit headers Table A 1 Jackrabbit Header Pin 1 Locations Header Description Pin 1 x y Coordinates J1 Power supply input 0 110 0 700 J2 External battery 0 415 0 638 J3 Programming port 0 145 0 149 J4 Jackrabbit subsystems 0 984 2 023 J5 Jackrabbit subsystems 3 184 2 023 3 3 84 0 9 23 0 2 0 5 2 5 64 2 28 58 0 15 dia 4x 4 3 5 89 2 5 64 0 53 14 0 59 15 0 96 25 0 53 14 0 59 15 0 96 25 ...

Page 33: ...y bit 15 CMOS level 8 are bytewide 7 are by bit Analog Inputs One low grade A D input input range 0 1 V to 2 8 V 9 bit resolution 8 bit accuracy 10 samples s Analog Outputs Two 9 bit filtered and buffered PWM outputs one 0 1 2 8 V DC one 0 7 3 5 V DC update rate 50 Hz Serial Ports Up to four serial ports two RS 232 or one RS 232 with CTS RTS rated at 15 kV ESD one RS 485 rated at 15 kV ESD RS 485 ...

Page 34: ...e A 2 shows the header and jumper locations used to configure the various Jackrabbit options Figure A 2 Location of Jackrabbit Configurable Positions R55 R56 D21 C27 D24 JP2 R16 R17 R18 JP1 Z World Inc JACKRABBIT JP3 Top Side Bottom Side CAUTION Battery ...

Page 35: ... introduced in 2003 Table A 3 Jackrabbit Jumper Configurations Header Description Pins Connected Factory Default JP1 SRAM Size n c 32K 1 2 128K 2 3 512K JP2 Flash Memory Size 1 2 128K 256K 2 3 512K JP3 Flash Memory Bank Select 1 2 Normal Mode 2 3 Bank Mode HV3 Sinking Sourcing D21 R55 Sinking R56 Sourcing RS 485 Bias and Termination Resistors not isnatlled on BL1820 R17 Termination resistor R16 R1...

Page 36: ...fects of moisture and contaminants over time and helps to maintain the accuracy of the real time clock Figure A 3 Jackrabbit Areas Receiving Conformal Coating Any components in the conformally coated area may be replaced using standard soldering procedures for surface mounted components A new conformal coating should then be applied to offer continuing protection against the effects of moisture an...

Page 37: ...d by the RS 485 chip on BL1800 and BL1810 models and five are outputs only one of which is used by the RS 485 chip on BL1800 and BL1810 models as shown in Figure A 4 Figure A 4 Jackrabbit Subsystems JACKRABBIT Port A Port B Port D Port E Serial Ports Programming Port PA0 PA7 PB0 PB5 PB6 PB7 HV0 HV3 2x RS 232 1x RS 485 CMOS synch ronous serial PE4 PE5 PD0 PD3 PD6 PD7 DA0 DA1 AD0 PCLK IOBENB Watchdo...

Page 38: ...port clock CLKB PB1 CLKA is connected to J3 programming port PB1 Input Serial port clock CLKA PB2 Input Slave port write SWR PB3 Input Slave port read SRD PB4 Input Slave port address lines SA1 SA0 PB5 Input PB6 Output PB7 Output Slave port attention line SLAVEATTN PC0 Output TXD Connected to RS 485 IC Tx input PC1 Input RXD Connected to RS 485 IC Rx output PC2 Output TXC Connected to RS 232 IC Tx...

Page 39: ...ected to RS 485 IC data enable input PD6 ATXA output PD7 ARXA input PE0 Bitwise or parallel programmable I O I0 output or INT0A input HV0 output control PE1 I1 output or INT1A input HV1 output control PE2 I2 output HV2 output control PE3 I3 output HV3 output control PE4 I4 output or external INT0B input PE5 I5 output or external INT1B input PE6 I6 output Connected to A D comparator output PE7 I7 o...

Page 40: ...he slave port of the Rabbit 2000 microprocessor The primary function of PCLK is as a peripheral clock or a peripheral clock 2 but PCLK can instead be used as a digital output Similarly IOBENB is an I O buffer enable but can instead be used as a digital output STAT and WDO also have limited uses as digital outputs ...

Page 41: ...ENDIX B PROTOTYPING BOARD Appendix B describes the features and accessories of the Proto typing Board and explains the use of the Prototyping Board to demonstrate the Jackrabbit and to build prototypes of your own circuits ...

Page 42: ...PD4 PD2 DA0 AD0 PC6 PC4 PD0 PC5 PC7 AGND DA1 PD1 PD3 PD5 PD7 GND 485 VCC SM1 STAT VBAT GND 9 5 6 1 J4 Buzzer Top Side Bottom Side J6 J1 J7 J2 J5 J3 JP1 JP2 1 2 3 R3 R1 LS1 S2 S1 DS1 DS2 DS3 RT1 S4 S3 DS9 DS4 DS5 DS6 DS7 DS8 RN1 S5 PC2 PC0 TXB RXB VCC GND RXC TXC PC1 PC3 TXC RXC RXB TXB GND JACKRABBIT PROTOTYPING BOARD GND PA6 PA4 PA2 PA0 PA7 PA5 PA3 PA1 6 9 5 J4 VCC 1 GND PE2 PE4 PE6 PE0 HV0 HV2 K...

Page 43: ... DS8 S1 S2 S3 S4 GND GND PB5 PB4 PB3 PB2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 GND PE2 PE4 PE6 PE0 HV0 HV2 K GND WDO PB6 PB4 PB2 PB0 GND VCC RAW HV3 HV1 GND PE1 PE3 PE5 PE7 PCLK PB7 PB5 PB3 PB1 GND BZR VCC K AD0 PD0 PE4 POT RAW HV0 COIL COIL JP2 N C COM N O RST GND IOBEN SM0 VCC 485 GND PD6 PD4 PD2 DA0 AD0 PC6 PC4 PD0 PC5 PC7 AGND DA1 PD1 PD3 PD5 PD7 GND 485 VCC SM1 STAT VBAT GND 9 5 6 1 J4 Buzzer J1 JP...

Page 44: ...you may connect COIL to RAW If you use another power supply connect COIL to 12 V if RAW is different NOTE If you do use the transformer supplied with the Development Kit for COIL be aware that its voltage may be as high as 16 V at low current draws This needs to be taken into consideration if you plan to use a 12 V relay in critical applications Relay Contacts 0 156 4 mm spacing COIL and COIL spac...

Page 45: ...ping Board to an available DE9 PC serial port Unlike the CMOS level signals on header J3 the programming port on the Jackrabbit board the sig nals on header J1 on the Prototyping Board are full RS 232 level signals without needing the CMOS to RS 232 converter that is present in the program ming cable The RS 232 level signals are processed via the MAX232 transceiver chip U4 on the Jack rabbit board...

Page 46: ... spe cific demonstration hardware later if needed Each pin is labeled on the PCB to facilitate placing the jumpers The jumper positions are summarized in Table B 1 Table B 1 Prototyping Board Jumper Settings Header JP1 Header JP2 continued Pins Description Pins Description 1 2 Buzzer 5 6 PA2 to LED DS3 3 5 K to 5 V 7 8 PA3 to LED DS4 5 6 K to RAW 9 10 PA4 to LED DS5 7 8 Potentiometer or Thermistor...

Page 47: ...tion is routed to its unique set of connection holes Because the traces are very thin carefully determine which set of holes is connected to which surface mount pad There are several standard 0805 passive component surface mount pads These pads are not routed to wir ing holes so wire must be soldered directly to the component In addition there is a large generic array of wide traces connected to l...

Page 48: ...44 Jackrabbit BL1800 ...

Page 49: ...chematic The external power RAW is provided to any daughterboard connected to the Jackrabbit via pin 38 of header J4 RAW is not protected against reversed polarity such as could happen if the cable was connected to header J1 offset by one pin This absence of protec tion is intentional so as to provide the maximum possible voltage to any daughterboard connected to the Jackrabbit Capacitor C1 provid...

Page 50: ...c The linear regulator maintains its output voltage to within 5 as long as the heat sink is dissipating less than 2 W The regulator will operate outside its specifications when the heat sink is dissipating 2 W to 3 3 W Thermal shutdown turns the regulator off above 3 3 W Figure C 2 shows the power operating curves Figure C 2 7805 Linear Regulator Power Operating Curve The Jackrabbit operating at 1...

Page 51: ...o 40 V Figure C 3 shows typical power operating curves for both the linear regulator BL1810 and BL1820 and the switching regulator BL1800 for a nonloaded Jackrabbit operating at 14 7 MHz with the programming cable connected Figure C 3 Typical Jackrabbit Current Consumption 5 10 15 20 25 30 35 125 100 75 50 25 0 Current mA DCIN V 40 Switching regulator BL1800 29 49 MHz Linear regulator BL1810 and B...

Page 52: ...life of the battery is 10 years the battery can last for its full shelf life when external power is applied to the Jackrabbit Header J2 shown in Figure C 4 allows external access to the battery This header makes it possible to connect an external 3 V power supply while replacing the soldered in 3 V lithium coin type battery This allows the Jackrabbit SRAM and real time clock to retain data while t...

Page 53: ...der between the battery voltage and the tem perature compensation voltage at the anode of diode D80 This voltage divider biases the base of Q1 to about 2 6 V VBE on Q1 is about 0 55 V Therefore VRAM is about 2 05 V These voltages vary with temperature VRAM varies the least because temperature com pensation diodes D80 D82 will offset the variation with temperature of Q1 VBE R80 R82 may be stuffed i...

Page 54: ...ntly different voltage than VRAM When the Jackrabbit is not resetting pin 2 on U21 is high the RES line will be high This turns on Q24 causing its collector pin 3 to go low This turns on Q23 allowing VRAM to nearly equal Vcc When the Jackrabbit is resetting the RES line will go low This turns off Q23 and Q24 providing an isolation between Vcc and VRAM The battery backup circuit keeps VRAM from dro...

Page 55: ...ishes this task for the CS signal line In a powered up condition the CS control circuit must allow the processor s chip select signal CS1 to control the SRAM s CS signal CSRAM So with power applied CSRAM must be the same signal as CS1 and with power removed CSRAM must be held high but only needs to be battery voltage high Q20 and Q21 are MOSFET transistors with opposing polarity They are both turn...

Page 56: ... high on the processor s reset line RES When the Jackrabbit is not in reset the reset line will be high turning on N channel Q20 and Q22 Q22 is a simple inverter needed to turn on Q21 an P channel MOSFET When a reset occurs the RES line will go low This will cause C23 to discharge through R42 and R40 This small delay about 160 µs ensures that there is adequate time for the processor to write any l...

Page 57: ...cable The PROG connector is used only when the programming cable is attached to the programming connector header J3 while a new application is being devel oped Otherwise the DIAG connector on the programming cable allows the programming cable to be used as an RS 232 to CMOS level converter for serial communication which is appropriate for monitoring or debugging a Jackrabbit system while it is run...

Page 58: ...not connected to this connector The programming port is then enabled as a diagnostic port by polling the port periodically to see if communication needs to begin or to enable the port and wait for interrupts The pull up resistors on RXA and CLKA prevent spurious data reception that might take place if the pins floated If the clocked serial mode is used the serial port can be driven by having two t...

Page 59: ...erfect Bugs are always present in a system of any size In order to prevent danger to life or property it is the responsibility of the system designer to incorporate redundant protective mechanisms appropriate to the risk involved All Z World products are 100 percent functionally tested Additional testing may include visual quality con trol inspections or mechanical defects analyzer inspections Spe...

Page 60: ...56 Jackrabbit BL1800 ...

Page 61: ...ations 28 jumper configurations 30 31 HV3 sinking sourcing 31 JP1 SRAM size 23 31 JP2 flash memory size 31 JP3 flash memory bank se lect 23 31 jumper locations 30 Prototyping Board 42 RS 485 bias and termination resistors 31 M manuals 3 P pinout Jackrabbit 8 programming port 54 Prototyping Board 43 power supplies current consumption 47 voltage regulators 45 linear regulator 46 programming cable DI...

Page 62: ...58 Jackrabbit BL1800 ...

Page 63: ...pdf 090 0128 Programming Cable Schematic www zworld com documentation schemat 090 0128 pdf The schematics included with the printed manual were the latest revisions available at the time the manual was last revised The online versions of the manual contain links to the latest revised schematic on the Web site You may also use the URL information provided above to access the latest schematics direc...

Page 64: ...60 Jackrabbit BL1800 ...

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