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Manual VIPA System 200V 

Chapter 3   Deployment CPU 21x-2BS03 

HB97E - CPU - RE_21x-2BS03 - Rev. 15/16 

 

3-1 

Chapter 3  

Deployment CPU 21x-2BS03 

 

This chapter describes the deployment of the CPU in the System 200V. 
The description refers directly to the CPU and to the deployment in 
connection with peripheral modules, mounted on a profile rail together with 
the CPU at the backplane bus. 

 

 

Topic     

Page 

Chapter 3

 

Deployment CPU 21x-2BS03 .......................................... 3-1

 

Assembly.............................................................................................. 3-2

 

Start-up behavior.................................................................................. 3-2

 

Addressing ........................................................................................... 3-3

 

Hints for the deployment of the MPI interface ....................................... 3-5

 

Hardware configuration - CPU.............................................................. 3-6

 

Hardware configuration - I/O modules .................................................. 3-8

 

Setting CPU parameters....................................................................... 3-9

 

Project transfer................................................................................... 3-13

 

Operating modes................................................................................ 3-17

 

Overall reset....................................................................................... 3-19

 

Firmware update ................................................................................ 3-21

 

Factory reset ...................................................................................... 3-23

 

VIPA specific diagnostic entries.......................................................... 3-24

 

Using test functions for control and monitoring of variables ................ 3-26

 

 

Overview 

Content 

Summary of Contents for VIPA System 200V

Page 1: ...VIPA System 200V CPU Manual HB97E_CPU RE_21x 2BS03 Rev 15 16 April 2015 ...

Page 2: ...isions Conformity is indicated by the CE marking affixed to the product Conformity Information For more information regarding CE marking and Declaration of Conformity DoC please contact your local VIPA customer service organization Trademarks VIPA SLIO System 100V System 200V System 300V System 300S System 400V System 500S and Commander Compact are registered trademarks of VIPA Gesellschaft für Vi...

Page 3: ...oyment CPU 21x 2BS03 3 1 Assembly 3 2 Start up behavior 3 2 Addressing 3 3 Hints for the deployment of the MPI interface 3 5 Hardware configuration CPU 3 6 Hardware configuration I O modules 3 8 Setting CPU parameters 3 9 Project transfer 3 13 Operating modes 3 17 Overall reset 3 19 Firmware update 3 21 Factory reset 3 23 VIPA specific diagnostic entries 3 24 Using test functions for control and m...

Page 4: ...Contents Manual VIPA System 200V ii HB97E CPU RE_21x 2BS03 Rev 15 16 ...

Page 5: ...he general technical data of System 200V will be found Chapter 2 Hardware description Here the hardware components of the CPU are described The technical data are at the end of the chapter Chapter 3 Deployment CPU 21x 2BS03 This chapter describes the deployment of the CPU in the System 200V The description refers directly to the CPU and to the deployment in connection with peripheral modules mount...

Page 6: ...apters Every chapter provides a self contained description of a specific topic The following guides are available in the manual an overall table of contents at the beginning of the manual an overview of the topics for every chapter The manual is available in printed form on paper in electronic form as PDF file Adobe Acrobat Reader Important passages in the text are highlighted by following icons a...

Page 7: ... The manual must be available to all personnel in the project design department installation department commissioning operation The following conditions must be met before using or commissioning the components described in this manual Hardware modifications to the process control system should only be carried out when the system has been disconnected from power Installation and hardware modificati...

Page 8: ...Safety information Manual VIPA System 200V 4 HB97E CPU RE_21x 2BS03 Rev 15 16 ...

Page 9: ...formation required to assemble and wire a controller system consisting of System 200V components Besides the dimensions the general technical data of System 200V will be found Topic Page Chapter 1 Basics and Assembly 1 1 Safety Information for Users 1 2 System conception 1 3 Dimensions 1 5 Installation 1 7 Demounting and module exchange 1 11 Wiring 1 12 Installation guidelines 1 14 General data 1 ...

Page 10: ...ts thereby causing the module to become inoperable or unusable Modules that have been damaged by electrostatic discharges can fail after a temperature change mechanical shock or changes in the electrical load Only the consequent implementation of protection devices and meticulous attention to the applicable rules and regulations for handling the respective equipment can prevent failures of electro...

Page 11: ...tion modules Power supplies Extension modules CPU 214 M P I PW SF FC MC R S RN ST MR MMC 2 1 2 DC 24V X1 VIPA 214 1BC03 X 2 3 4 PW ER RD DE IM 253DP ADR X 8 9 10 VIPA 253 1DP00 1 2 DC 24V X1 D P 9 9 With a head module CPU respectively bus interface and DC 24V power supply are integrated to one casing Via the integrated power supply the CPU respectively bus interface is power supplied as well as th...

Page 12: ...g 2 or 3wire con nection facilities The modules are not connected to the backplane bus Profile rail 35mm Dimensions of the basic enclosure 1tier width HxWxD in mm 76x25 4x74 in inches 3x1x3 2tier width HxWxD in mm 76x50 8x74 in inches 3x2x3 Please note that you can only install header modules like the CPU the PC and couplers at slot 1 or 1 and 2 for double width modules 1 Head module double width ...

Page 13: ... Rev 15 16 1 5 Dimensions 1tier width HxWxD in mm 76 x 25 4 x 74 2tier width HxWxD in mm 76 x 50 8 x 74 80 mm 60 mm 74 mm 88 mm ca 110 mm 84 mm 85 mm 76 62 mm 76 mm 2 77 cm 24 mm Dimensions Basic enclosure Installation dimensions Installed and wired dimensions In Output modules ...

Page 14: ...em 200V 1 6 HB97E CPU RE_21x 2BS03 Rev 15 16 84 46 mm 88 mm 4 66 mm 27 mm 8 cm 76 mm 24 mm 11 mm 85 mm 89 mm 89 mm 27 mm 8 cm 76 mm 12 cm 125 mm 91 mm 65 mm 24 mm 5 mm 11 mm 85 mm Function modules Extension modules CPUs here with EasyConn from VIPA ...

Page 15: ... profile rail Length 2000mm height 15mm 290 1AF30 35mm profile rail Length 530mm height 15mm System 200V modules communicate via a backplane bus connector The backplane bus connector is isolated and available from VIPA in of 1 2 4 or 8tier width The following figure shows a 1tier connector and a 4tier connector bus The bus connector is to be placed on the profile rail until it clips in its place a...

Page 16: ... rails 1 Header module double width 2 Header module single width 3 Peripheral module PW ER RD BA ADR DC24V 1 2 0 1 1 2 4 3 PW SF FC MC MMC R S 4 Guide rails Use bus connectors as long as possible Sort the modules with a high current consumption right beside the header module In the service area of www vipa com a list of current consumption of every System 200V module can be found Installation on a...

Page 17: ...nstall or remove any modules Make sure that a clearance of at least 60mm exists above and 80mm below the middle of the profile rail Every row must be completed from left to right and it has to start with a header module 1 Header module double width 2 Header module single width 1 2 4 3 3 Peripheral modules 4 Guide rails Modules are to be installed side by side Gaps are not permitted between the mod...

Page 18: ... outer left location with the installation of your header module and install the peripheral modules to the right of this 1 Header module double width 2 Header module single width 3 Peripheral module 1 2 4 3 4 Guide rails Insert the module that you are installing into the profile rail at an angle of 45 degrees from the top and rotate the module into place until it clicks into the profile rail with ...

Page 19: ...or and pulling the connector The casing of the module has a spring loaded clip at the bottom by which the module can be removed The clip is unlocked by pressing the screwdriver in an upward direction Withdraw the module with a slight rotation to the top Attention Power must be turned off before modules are installed or removed Please regard that the backplane bus is interrupted at the point where ...

Page 20: ...to screw terminal connections spring clip wiring is vibration proof The assignment of the terminals is contained in the description of the respective modules You may connect conductors with a diameter from 0 08mm2 up to 2 5mm2 max 1 5mm2 for 18pole connectors The following figure shows a module with a 10pole connector 1 2 3 4 5 6 7 8 9 1 0 1 2 3 3 4 5 1 1 1 2 3 4 5 6 7 8 9 1 0 2 1 2 3 4 5 Locking ...

Page 21: ...iring procedure from top view Insert a screwdriver at an angel into the square opening as shown Press and hold the screwdriver in the opposite direction to open the contact spring Insert the stripped end of the wire into the round opening You can use wires with a diameter of 0 08mm2 to 2 5mm2 1 5mm2 for 18pole connectors By removing the screwdriver the wire is connected safely with the plug connec...

Page 22: ...All System 200V components are developed for the deployment in hard industrial environments and fulfill high demands on the EMC Nevertheless you should project an EMC planning before installing the components and take conceivable interference causes into account Electromagnetic interferences may interfere your control via different ways Electromagnetic fields RF coupling Magnetic fields with power...

Page 23: ...for details see below Analog lines must be laid isolated When transmitting signals with small amplitudes the one sided laying of the isolation may be favorable Lay the line isolation extensively on an isolation protected earth con ductor rail directly after the cabinet entry and fix the isolation with cable clamps Make sure that the isolation protected earth conductor rail is connected impedance l...

Page 24: ...ation one sided Then you only achieve the absorption of the lower frequencies A one sided isolation connection may be convenient if the conduction of a potential compensating line is not possible analog signals some mV res µA are transferred foil isolations static isolations are used With data lines always use metallic or metalized plugs for serial couplings Fix the isolation of the data line at t...

Page 25: ...nclosure 1tier width HxWxD in mm 76x25 4x74 in inches 3x1x3 2tier width HxWxD in mm 76x50 8x74 in inches 3x2x3 Wiring by means of spring pressure connections CageClamps at the front facing connector core cross section 0 08 2 5mm2 or 1 5mm2 18pole plug Complete isolation of the wiring when modules are exchanged Every module is isolated from the backplane bus Structure dimensions Reliability ...

Page 26: ...2 0 60 C Vertical installation EN 61131 2 0 60 C Air humidity EN 60068 2 30 RH1 without condensation rel humidity 10 95 Pollution EN 61131 2 Degree of pollution 2 Mechanical Oscillation EN 60068 2 6 1g 9Hz 150Hz Shock EN 60068 2 27 15g 11ms Mounting conditions Mounting place In the control cabinet Mounting position Horizontal and vertical EMC Standard Comment Emitted interference EN 61000 6 4 Clas...

Page 27: ...21x 2BS03 Rev 15 16 2 1 Chapter 2 Hardware description Here the hardware components of the CPU are described The technical data are at the end of the chapter Topic Page Chapter 2 Hardware description 2 1 Properties 2 2 Structure 2 3 Technical data 2 7 Overview Contents ...

Page 28: ...t for user program Battery backed clock MP2 I interface for data transfer Status LEDs for operating mode and diagnostics Serial Communication via 2x RS232 interface PW SF FC MC DC 24V 1 2 RN ST MR X1 MMC R S X 2 3 4 VIPA 214 2BS03 M P I 2 RN ER1 Rx1 Tx1 C O M 2 ER2 Rx2 Tx2 C O M 1 CPU 214SER PW SF FC MC DC 24V 1 2 RN ST MR X1 MMC R S X 2 3 4 VIPA 215 2BS03 M P I 2 RN ER1 Rx1 Tx1 C O M 2 ER2 Rx2 Tx...

Page 29: ...w CPU 21xSER PW SF FC MC DC 24V 1 2 RN ST MR X1 MMC R S X 2 3 4 VIPA 21x 2BS03 M P I 2 RN ER1 Rx1 Tx1 C O M 2 ER2 Rx2 Tx2 C O M 1 4 5 3 1 6 8 2 7 CPU 21xSER 8 RS232 interface COM2 MP I 2 5 4 3 2 1 9 8 7 6 reserved M24V RxD TxD P line B RTS M5V P5V P24V RxD TxD N line A n c 1 2 3 4 5 6 7 8 9 1 2 DC 24 V 0 V X1 1 2 3 4 5 6 7 8 9 COM1 RS232 CD RxD TxD DTR GND DSR RTS CTS RI 1 2 3 4 5 6 7 8 9 1 2 3 4 ...

Page 30: ...rovides the link for the data transfer between the CPU and the PC Via bus communication you are able to exchange programs and data between different CPUs that are linked over MPI For a serial exchange between the partners you normally need a special MPI converter But now you are also able to use the VIPA Green Cable Order No VIPA 950 0KB00 which allows you to establish a serial peer to peer connec...

Page 31: ...ject there exists You may install a VIPA MMC memory card in this slot as external storage device Order No VIPA 953 0KX10 The access to the MMC takes always place after an overall reset A rechargeable battery is installed on every CPU 21x to safeguard the contents of the RAM when power is removed This battery is also used to buffer the internal clock The rechargeable battery is maintained by a char...

Page 32: ...fect FC yellow Is turned on when variables are forced fixed MC yellow This LED blinks when the MMC is accessed The LEDs of the RS232 interfaces are located in the left half of the front panel and they are used for diagnostic purposes The following table shows the color and the significance of these LEDs Name Color Description RN green Communication processor runs ER1 red Error Interface 1 Rx1 gree...

Page 33: ...odules 32 Operable communication modules PtP 32 Operable communication modules LAN Command processing times Bit instructions min 0 18 µs Word instruction min 0 78 µs Double integer arithmetic min 1 8 µs Floating point arithmetic min 40 µs Timers Counters and their retentive characteristics Number of S7 counters 256 S7 counter remanence adjustable 0 up to 64 S7 counter remanence adjustable C0 C7 Nu...

Page 34: ...t 128 Byte Output process image preset 128 Byte Input process image maximal 128 Byte Output process image maximal 128 Byte Digital inputs 8192 Digital outputs 8192 Digital inputs central 512 Digital outputs central 512 Integrated digital inputs Integrated digital outputs Analog inputs 512 Analog outputs 512 Analog inputs central 128 Analog outputs central 128 Integrated analog inputs Integrated an...

Page 35: ...nsmission speed max 187 5 kbit s Point to point communication PtP communication 9 Interface isolated RS232 interface 9 RS422 interface RS485 interface Connector Sub D 9 pin male Transmission speed min 150 bit s Transmission speed max 115 2 kbit s Cable length max 15 m Point to point protocol ASCII protocol 9 STX ETX protocol 9 3964 R protocol 9 RK512 protocol 9 USS master protocol Modbus master pr...

Page 36: ...and processing times Bit instructions min 0 18 µs Word instruction min 0 78 µs Double integer arithmetic min 1 8 µs Floating point arithmetic min 40 µs Timers Counters and their retentive characteristics Number of S7 counters 256 S7 counter remanence adjustable 0 up to 64 S7 counter remanence adjustable C0 C7 Number of S7 times 256 S7 times remanence adjustable 0 up to 128 S7 times remanence adjus...

Page 37: ...al inputs 8192 Digital outputs 8192 Digital inputs central 512 Digital outputs central 512 Integrated digital inputs Integrated digital outputs Analog inputs 512 Analog outputs 512 Analog inputs central 128 Analog outputs central 128 Integrated analog inputs Integrated analog outputs Communication functions PG OP channel 9 Global data communication 9 Number of GD circuits max 4 Size of GD packets ...

Page 38: ... communication PtP communication 9 Interface isolated RS232 interface 9 RS422 interface RS485 interface Connector Sub D 9 pin male Transmission speed min 150 bit s Transmission speed max 115 2 kbit s Cable length max 15 m Point to point protocol ASCII protocol 9 STX ETX protocol 9 3964 R protocol 9 RK512 protocol 9 USS master protocol Modbus master protocol Modbus slave protocol Special protocols ...

Page 39: ...ile rail together with the CPU at the backplane bus Topic Page Chapter 3 Deployment CPU 21x 2BS03 3 1 Assembly 3 2 Start up behavior 3 2 Addressing 3 3 Hints for the deployment of the MPI interface 3 5 Hardware configuration CPU 3 6 Hardware configuration I O modules 3 8 Setting CPU parameters 3 9 Project transfer 3 13 Operating modes 3 17 Overall reset 3 19 Firmware update 3 21 Factory reset 3 23...

Page 40: ...ttery may be totally discharged This means that the battery buffered RAM is deleted In this state the CPU executes an overall reset because with an empty battery the RAM content is undefined If a MMC with a S7PROG WLD is plugged program code and data blocks are transferred from the MMC into the work memory of the CPU If there is no MMC the project from the internal Flash is loaded Depending on the...

Page 41: ... 0 127 are additionally saved in a special memory area called the process image The process image is divided into two parts process image of the inputs PII process image of the outputs PIQ Peripheral area 0 127 128 1023 Process image 0 127 0 127 Inputs PII Outputs PIQ Digital modules Analog modules The process image is updated automatically when a cycle has been completed You may access the module...

Page 42: ... area rel Addr Output byte 1 Output byte 2 Output byte 3 Output byte 127 Output byte 0 Output byte 7 Output byte 8 Output byte 9 Output byte 1023 0 1 2 3 127 128 135 136 137 1023 analog digital PIQ 0 1 2 3 127 PII Slot 1 2 3 4 5 6 You may change the allocated addresses at any time by means of the Siemens SIMATIC manager In this way you may also change the addres ses of analog modules to the range ...

Page 43: ...nt of MPI cables Deploying MPI cables at the CPUs from VIPA you have to make sure that Pin 1 is not connected This may cause transfer problems and in some cases damage the CPU Especially PROFIBUS cables from Siemens like e g the 6XV1 830 1CH30 must not be deployed at MP2 I jack For damages caused by nonobservance of these notes and at improper deployment VIPA does not take liability For the serial...

Page 44: ...be fulfilled for project engineering The Siemens SIMATIC manager is installed at PC respectively PU The GSD files have been included in Siemens hardware configurator Serial connection to the CPU e g MPI Adapter Note The configuration of the CPU requires a thorough knowledge of the Siemens SIMATIC manager and the hardware configurator Go to www vipa com Service Download PROFIBUS GSD files and downl...

Page 45: ...the hardware configurator from Siemens with a new project Insert a profile rail from the hardware catalog Place at slot 2 the following CPU from Siemens CPU 315 2DP 315 2AF03 0AB00 V1 2 For the System 200V create a new PROFIBUS subnet Attach the slave system VIPA_CPU21x to the subnet with PROFIBUS Address 1 After installing the vipa_21x gsd the slave system may be found at the hardware catalog at ...

Page 46: ... 21x PB Addr 1 PB Addr 2 1 VIPA_CPU CPU21x CPU 214 PW SF FC MC R S RN ST MR MMC 2 Module CPU 315 2DP DP Slot 1 2 X2 3 PROFIBUS 1 DP master system 1 For parameterization double click during the project engineering at the slot overview on the module you want to parameterize In the appearing dialog window you may set the wanted parameters By using the SFCs 55 56 and 57 you may alter and transfer para...

Page 47: ...cription of the Siemens CPU 315 2AF03 is CPU 315 2DP Order number and firmware are identical to the details in the hardware catalog window The Name field provides the short description of the CPU If you change the name the new name appears in the Siemens SIMATIC manager In this field information about the module may be entered If the checkbox for Startup when expected actual configuration differ i...

Page 48: ... an error in the CPU program This parameter is not relevant Using this parameter you can control the duration of communication processes which always extend the scan cycle time so it does not exceed a specified length If the cycle load from communication is set to 50 the scan cycle time of OB 1 can be doubled At the same time the scan cycle time of OB 1 is still being influenced by asynchronous ev...

Page 49: ...g OB is deactivated Activate the check box of the time of day interrupt OBs if these are to be automatically started on complete restart Select how often the interrupts are to be triggered Intervals ranging from every minute to yearly are available The intervals apply to the settings made for start date and time Enter date and time of the first execution of the time of day interrupt This parameter...

Page 50: ...og interrupts are enabled Phase offset allows to distribute processing time for watchdog interrupts across the cycle This parameter is not supported Here 1 of 3 protection levels may be set to protect the CPU from unauthorized access Protection level 1 default setting No password adjustable no restrictions Protection level 2 with password Authorized users read and write access Unauthorized user re...

Page 51: ...RS485 jack Every bus participant identifies itself at the bus with an unique address in the course of the address 0 is reserved for programming devices A cable has to be terminated with its surge impedance For this you switch on the terminating resistor at the first and the last participant of a network or a segment Please make sure that the participants with the activated terminating resistors ar...

Page 52: ...ect in the SIMATIC manager from Siemens Choose in the menu Options Set PG PC interface Select in the according list the PC Adapter MPI if appropriate you have to add it first then click on Properties Set in the register MPI the transfer parameters of your MPI net and type a valid address Switch to the register Local connection Set the COM port of the PC and the transfer rate 38400Baud for the MPI ...

Page 53: ...pplication you may update the firmware of all recent VIPA CPUs with MP2 I jack and certain field bus masters see Note Important notes for the deployment of the Green Cable Nonobservance of the following notes may cause damages on system components For damages caused by nonobservance of the following notes and at improper deployment VIPA does not take liability Note to the application area The Gree...

Page 54: ...h user program is plugged in AUTOLOAD WLD is read after PowerON from the MMC and transferred into the battery buffered RAM During the transfer the MC LED blinks Please regard that your user memory serves for enough space otherwise your user program is not completely loaded and the SF LED gets on Execute a compression before the transfer for this does not happen automatically When the MMC has been ...

Page 55: ... transition from STOP to RUN the system calls the start up organization block OB 100 The processing time for this OB is not monitored The start up OB may issue calls to other blocks All digital outputs are disabled during the start up i e outputs are inhibited RUN LED blinks as soon as the OB 100 is operated and for at least 3s even if the start up time is shorter or the CPU gets to STOP due to an...

Page 56: ...s 0 20mA issue 0mA Current outputs 4 20mA issue 4mA If configured also substitute values may be issued decentral outputs Same behavior as the central digital analog outputs decentral inputs The inputs are cyclically be read by the decentra lized station and the recent values are put at disposal STOP RUN res PowerON general First the PII is deleted then OB 100 is called After the execution of the O...

Page 57: ...ve been cleared from the CPU Condition The operating mode of the CPU is STOP Place the function selector on the CPU in position ST the S LED is on Overall reset Place the function selector in the position MR and hold it in this position for app 3 seconds The S LED changes from blinking to permanently on Place the function selector in the position ST and switch it to MR and quickly back to ST withi...

Page 58: ...our CPU in STOP mode and start the overall reset if this has not been done as yet The S LED blinks during the overall reset procedure When the S LED is on permanently the overall reset procedure has been completed At this point the CPU attempts to reload the parameters and the program from the memory card The MC LED is on When the reload has been completed the LED expires The operating mode of the...

Page 59: ... label on the rear of the module indicates the firmware version You may display the current firmware version of your CPU via the Siemens SIMATIC manager To display the firmware version you go online with the CPU via your PG or PC and start the Siemens SIMATIC manager Via PLC Module status register General the current firmware version is evaluated and displayed Go to www vipa com Click on Service D...

Page 60: ...he MMC 3 You start the transfer of the firmware as soon as you tip the operating mode switch lever downwards to MR within 10s and leave it in ST position 4 During the update process the LEDs SF and FC are alternately blinking and MC LED is on This may last several minutes 5 The update is successful finished when the LEDs PW S SF FC and MC are on If they are blinking fast an error occurred 6 Turn P...

Page 61: ... Starting here count the static light states of the S LED 3 After the 6 static light release the operating mode switch and tip it downwards to MR Now the RUN LED lights up once This means that the RAM was deleted completely 4 For the confirmation of the resetting procedure the LEDs PW and S are on 5 Then you have to switch the power supply off and on The proceeding is shown in the following Illust...

Page 62: ...choose the option PLC Module Information in the Siemens SIMATIC manager Via the register Diagnostic Buffer you reach the diagnostic window Module information Diagnostic Buffer Nr 8 9 10 11 12 13 Time of day 13 18 11 370 Date 19 12 2011 Event Event ID 16 E0CC Path Accessible Nodes MPI 2 Operating mode CPU RUN Details VIPA ID The diagnosis is independent from the operating mode of the CPU You may st...

Page 63: ...ve configuration 0xE012 Error at parameterization 0xE013 Error at shift register access to VBUS digital modules 0xE014 Error at Check_Sys 0xE015 Error at access to the master Zinfo2 Slot of the master 32 page frame master 0xE016 Maximum block size at master transfer exceeded Zinfo1 I O address Zinfo2 Slot 0xE017 Error at access to integrated slave 0xE018 Error at mapping of the master I O devices ...

Page 64: ...xecuted It is also possible to enter corrections to the program Note When using the test function Monitor the PLC must be in RUN mode The processing of the states may be interrupted by means of jump commands or by timer and process related alarms At the breakpoint the CPU stops collecting data for the status display and instead of the required data it only provides the PG with data containing the ...

Page 65: ...outputs It is possible to check the wiring and proper operation of output modules You can set outputs to any desired status with or without a control program The process image is not modified but outputs are no longer inhibited Control of variables The following variables may be modified I Q M T C and D The process image of binary and digital operands is modified independently of the operating mod...

Page 66: ...Chapter 3 Deployment CPU 21x 2BS03 Manual VIPA System 200V 3 28 HB97E CPU RE_21x 2BS03 Rev 15 16 ...

Page 67: ...f the serial RS232 interface of the CPU Here you ll find all information about the deployment of the serial interfaces of the CPU Topic Page Chapter 4 Serial communication 4 1 Fast introduction 4 2 Protocols and Procedures 4 4 RS232 interface 4 8 Communication 4 9 Initialize interfaces 4 11 Interface parameters 4 13 Interface communication 4 16 Overview Content ...

Page 68: ...a preceding RLO 1 result of logic operation otherwise they are not executed The internal CP of the CPU 21x 2BS03 is directly connected to the CPU part via a Dual Port RAM also called page frame This page frame is available at the CPU section as standard CP interface The data transfer happens via the standard handling blocks SEND RECEIVE and FETCH The communication via the according protocols is co...

Page 69: ...Rev 15 16 4 3 Depending to the protocol the following handling blocks are used ASCII STX ETX 3964 R RK512 SFC Name x x x SFC 230 SEND x x SFC 231 RECEIVE x SFC 232 FETCH x x x SFC 233 CONTROL x x x SFC 234 RESET x x x SFC 235 SYNCHRON x x x SFC 236 SEND_ALL x x x SFC 237 RECV_ALL ...

Page 70: ... protocol with start and end ID where STX stands for Start of Text and ETX for End of Text The STX ETX procedure is suitable for the transfer of ASCII characters 20h 7Fh It does not use block checks BCC Any data transferred from the periphery must be preceded by an Start followed by the data characters and the end character The effective data which includes all the characters between Start and End...

Page 71: ...racter only at 3964R NAK Negative Acknowledge only 3964R STX DLE Message data DLE ETX BCC Monitor delayed acknowledgment DLE Monitor delayed acknowledgment Active partner Passive partner You may transfer a maximum of 255Byte per message Note When a DLE is transferred as part of the information it is repeated to distinguish between data characters and DLE control characters that are used to establi...

Page 72: ...nt STX DLE Reaction message DLE ETX BCC DLE only 3964R Active partner Passive partner Monitor delayed acknowledgment Monitor delayed acknowledgment The coordination flag is set in the partner PLC in active mode when a message is being received This occurs for input as well as for output commands When the coordination flag has been set and a message with this flag is received then the respective da...

Page 73: ... is not equal to STX it will transmit a NAK The driver does not respond with an answer to the reception of a NAK When ZVZ expires during the reception the driver will send a NAK and wait for another connection request The driver also sends a NAK when it receives an STX while it is not ready The 3964R procedure appends a Block check character to safeguard the transmitted data The BCC Byte is calcul...

Page 74: ...r rate up to 57 6kBaud Via 9pin plug you may establish a serial point to point connection 9pin plug Connection RS232 Pin Description 1 CD 2 RxD 3 TxD 4 DTR 5 GND 6 DSR 7 RTS 8 CTS 9 RI The CPU 21x 2BS03 currently supports the following RS232 signals TxD Transmit Data The transmit data is transferred via the TxD line When the transmit line is not used the CPU 21x 2BS03 holds it at a logical 1 RxD R...

Page 75: ... Synchronization between CPU and CP and presetting of the block size SFC 230 SEND Initialize a send order SFC 236 SEND ALL Send user data SFC 231 RECEIVE Initialize a receive order SFC 237 RECEIVE ALL Receive user data SFC 232 FETCH Initialize a fetch order SFC 233 CONTROL Block for communication control SFC 234 RESET Deletes all orders and activates new parameter Depending to the protocol the fol...

Page 76: ... enter the wanted block size Page frame basic address 0 Block size PAFE Parameterize the interfaces with SEND SFC 230 with order no 201 and parameter DB To take over the parameters you call RESET SFC 234 with order no 0 Cycle OB1 Create SEND and RECEIVE orders for send and receive initialization Create SEND ALL and RECEIVE ALL orders for user data transfer A more detailed description follows Progr...

Page 77: ...out the block size Name Declaration Type Description SSNR IN INT Interface number BLGR IN INT Block size PAFE OUT BYTE Parameterization error Number of the logical interface page frame address to which the according order refers to SSNR must be 0 To avoid long cycle run times it is convenient to split large data amounts into smaller blocks for transmitting them between CP and CPU You declare the s...

Page 78: ...er 0 interrupts all orders and the previous parameters are activated Analog to SEND the block requires a preceding RLO 1 Name Declaration Type Description SSNR IN INT Interface number ANR IN INT Job number PAFE OUT BYTE Parameterization error CALL SFC 235 SYNCHRON SSNR 0 BLGR 6 PAFE MB199 SET RLO 1 CALL SFC 230 SEND parameter for COM1 SSNR 0 ANR 201 ID for parameterization IND 0 QANF P DB9 DBX0 0 ...

Page 79: ...vated MODI_1 Parameter following 0 81h 0 2 BYTE Baudrate BAUDRATE_DEF BAUDRATE_150 BAUDRATE_300 BAUDRATE_600 BAUDRATE_1K2 BAUDRATE_1K8 BAUDRATE_2K4 BAUDRATE_4K8 BAUDRATE_7K2 BAUDRATE_9K6 BAUDRATE_14K4 BAUDRATE_19K2 BAUDRATE_38K4 BAUDRATE_57K6 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 09h 3 BYTE DataBits DATABIT_5 DATABIT_6 DATABIT_7 DATABIT_8 0 1 2 3 3 4 BYTE Parity PARITY_NONE PARIT...

Page 80: ... 200 if PROTOCOL_STXETX Data byte Type Designator Values Default Transmit channel 8 9 WORD BufAnz 1 n 1 10 11 WORD BufSize 16 1024 256 12 13 WORD ZNA time delay after job 0 n 0 Start code 14 15 WORD Quantity 1 2 1 16 BYTE Code 1 0 255 STX 17 BYTE Code 2 0 255 STX End code 18 19 WORD Quantity 1 2 1 20 BYTE Code 1 0 255 ETX 21 BYTE Code 2 0 255 ETX Receive channel 22 23 WORD BufAnz 1 n 1 24 25 WORD ...

Page 81: ...L_3964 R _RK512 Data byte Type Designator Values Default Transmit receive channel 8 9 WORD BufAnz 1 n 1 10 11 WORD BufSize 16 1024 128 12 13 WORD ZNA time delay after job 0 n 0 14 15 WORD ZVZ char delay time 1 n 200 16 17 WORD QVZ ack delay time 1 n 500 18 19 WORD BWZ block delay time 1 n 10000 20 21 WORD STX number of retries connection set up 1 n 3 22 23 WORD DBL number of retries data blocks 1 ...

Page 82: ... RECEIVE orders for send and receive initialization Create SEND ALL and RECEIVE ALL orders for user data transfer The following section contains a summary of this blocks The SEND block serves the initialization of a send order to a CP Please regard that a send order is only executed when the following conditions are met the SEND has received a RLO 1 the bit order in process in the indicator word h...

Page 83: ... to data destination PAFE OUT BYTE Parameterization error ANZW IN_OUT DWORD Indicator word Via the RECEIVE_ALL block the data received from the CP is transmitted from the CP to the CPU by using the declared block size Location and size of the data area that is to transmit with RECEIVE_ALL must be declared before by calling RECEIVE In the indicator word that is assigned to the concerned order the b...

Page 84: ...owing conditions are met the FETCH has received a RLO 1 the bit order in process in the indicator word has been reset Name Declaration Type Description SSNR IN INT Interface number ANR IN INT Job number IND IN INT Mode of addressing ZANF IN ANY Pointer to data destination PAFE OUT BYTE Parameterization error ANZW IN_OUT DWORD Indicator word The purpose of the CONTROL block is the following Update ...

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