Yamaha RX-V3900, Service Manual

Page: 158 / 226

IC714
IC715
IC716
IC716
IC717
A
1
2
3
4
5
6
7
8
9
10
B C D E F G H I J K L M N
RX-V3900/DSP-AX3900
158
D-VIDEO 2/10
0
3.3
1.6
0
3.3
3.3 3.3 0 1.6
0.4 3.3 0.5 0.5 0.6 0 2.5 0 0 2.5 2.5 2.5 2.5 2.5 2.5 3.3 2.5 0 2.5 2.5
0
3.3 3.3
0 0
0 0 0 0
0.7 1.0 0.8 3.3 0.8 1.7 0 0.5 0.4 1.1 0 0 0 0 0 0
3.3
3.3
0
1.7
3.3
3.3
0
0
0
1.7
3.3
3.3
3.3
3.3
3.3
1.7
0
3.3
1.7
0
0
0
0
0
0
0
0
3.3
3.3
0.2
0.2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.5
0.5
3.3
0.5
0.5
1.3
0
0.5
0
0
0.5
1.4
0
3.3
0
0
3.1
3.2
0
0
3.3
0
3.3
3.3
1.7
3.3
0
0
0
0
0
0
0
3.3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.3
0
0
0
0
0
3.3
0
3.3
0
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
0 0
3.3
0
3.3
0
0
0.2
0 0 0 0 0 0 0
0.5 0.5 0.5 0.5 0.3 0.5
0
3.3 1.7
0 0
3.3
0
3.3
0
0 0 0 0 0 0 0 0 0
3.3
0
3.3
0
3.3
3.3
0
0
3.3
0 0
3.3
0 0 0 0
3.3
0.5 0 0 1.4 0 0 3.1 3.2 3.3 3.3 0 0 0 0 0 0 0 0 0.2 3.3 0
3.3 3.3 0 3.3
0
0 0
3.3 3.3
0 0
0.2
0 0 0
3.3
0
0 0
0 0
3.3
0 0 0 0 0 0 0
3.3 3.3
0 0
3.3 1.7
0
3.3
0
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
0
3.3
0
3.3
3.3
3.3
2.5
0
GUI PROCESSOR
64M bit SDRAM
FF
to D-VIDEO 1/10
to D-VIDEO 1/10
to D-VIDEO 1/10
to D-VIDEO 1/10
to D-VIDEO 6/10
to D-VIDEO 8/10
to D-VIDEO 8/10, 9/10
to D-VIDEO 8/10
to D-VIDEO 9/10
IC716 : TC7WZ04FK
Triple inverter
V
CC
3A
2Y
1A
GND
3Y
1
2
3
4
2A
1Y
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
IC717 : SN74LVC74APWR
Dual positive-edge-triggered D-type flip-flop
A23-2
D31-0
CPU
INTERFACE
CSREG
RD
A1
/
WR3
WR2-0
WAIT
SDRAM
INTERFACE
DRAWING
PROCESSOR
UNIT
PIXEL
DATA
CONTROLLER
CRT
CONTROLLER
DAC
HSYNC
CSYNC
VSIN
HSIN
SDQ31-0
SA12-0
SBA1-0
SDCLK
SCS
RAS
CAS
WE
DQM3-0
CSMEM
INT
RESET
DCKIN
DCKOUT
DRI[5:0]
DGI[5:0]
DBI[5:0]
DRO[5:0]
DGO[5:0]
DBO[5:0]
AT1-0
R, G, B
VIDEO
CAPTURE
CONTROLLER
GCKIN
GCKOUT
READY
SYCKIN
SYCKOUT
FSC
DREQ
IC714 : YGV619
OSD display controller
CLK
CS
RAS
CAS
WE
Command Decoder
Contr
ol Logic
Latch Cir
cuit
Input & Output
Buf
fer
Row Decoder
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQM0-3
DQ
CKE
Address
Clock
Generator
Row
Address
Buffer
Column
Address
Buffer
&
&
Refresh
Counter
Refresh
Counter
Mode
Register
Bank B
Bank C
Bank D
VDD
VDD
BA1
BA0
A10/AP
DQM2
A0
A1
A2
CS
RAS
CAS
WE
DQM0
VDD
NC
NC
NC
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDDQ
VDDQ
VSSQ
VDDQ
DQ23
DQ22
DQ21
DQ20
DQ19
DQ16
DQ17
DQ18
VDDQ
VSSQ
VSSQ
DQ0
VDD
VSS
A4
A5
A6
A7
A8
A3
A9
NC
DQ31
DQ30
DQ29
VSSQ
DQ28
DQ27
DQ26
DQ25
DQ24
CKE
CLK
DQM1
DQM3
VSS
VSS
VDDQ
VDDQ
VSSQ
VDDQ
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
NC
NC
NC
VSSQ
VSSQ
VDDQ
DQ15
VSS
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
70
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
IC715 : M12L64322A-7TG 0.1UM
512 k x 32-bit x 4 banks synchronous DRAM