Yamaha RX-V1900, Service Manual

Page: 83 / 198

RX-V1
90
0/HTR-6290/DSP-AX1
90
0
83
No.
F
unction Name
TYPE
(1)
PULL
(2)
GPIO
(3)
Detail of F
unction
64
EM_D[9]
IO
–
N
EMIF data bus [lower 16-Bits]
65
Cor
e Supply (CVpp)
66
EM_D[8]
IO
–
N
EMIF data bus [lower 16-bits]
67
EM_WE_DQM[1]
O
–
N
W
rite enable or byte enable for EM_D [15:8]
68
IO Supply (DVpp)
69
Gr
ound(Vss)
70
EM_CLK
O
–
N
SDRAM clock
71
EM_CKE
O
–
N
SDRAM clock enable
72
Gr
ound(Vss)
73
IO Supply (DVpp)
74
EM_A[11]
O
–
N
EMIF addr
ess bus
75
EM_A[9]
O
–
N
EMIF addr
ess bus
76
EM_A[8]
O
–
N
EMIF addr
ess bus
77
Cor
e Supply (CVpp)
78
Gr
ound(Vss)
79
EM_A[7]
O
–
N
EMIF addr
ess bus
80
EM_A[6]
O
–
N
EMIF addr
ess bus
81
IO Supply (DVpp)
82
Gr
ound(Vss)
83
EM_A[5]
O
–
N
EMIF addr
ess bus
84
EM_A[4]
O
–
N
EMIF addr
ess bus
85
Cor
e Supply (CVpp)
86
EM_A[3]
O
–
N
EMIF addr
ess bus
87
Gr
ound(Vss)
88
EM_A[2]
O
–
N
EMIF addr
ess bus
89
EM_A[1]
O
–
N
EMIF addr
ess bus
90
Cor
e Supply (CVpp)
91
EM_A[0]
O
–
N
EMIF addr
ess bus
92
IO Supply (DVpp)
93
EM_A[10]
O
–
N
EMIF addr
ess bus
94
EM_BA[1]
O
–
N
SDRAM bank addr
ess and asynchr
onous memor
y Low-Or
der
addr
ess
95
Gr
ound(Vss)
96
EM_BA[0]
O
–
N
SDRAM bank addr
ess and asynchr
onous memor
y Low-Or
der
addr
ess
97
EM_CS[0]
O
–
N
SDRAM chip select
98
EM_RAS
O
–
N
SDRAM r
ow addr
ess str
obe
99
Gr
ound(Vss)
100
EM_CS[2]
O
–
N
Asynchr
onous memor
y chip Select
101
Cor
e Supply (CVpp)
102
EM_R
W
O
–
N
Asynchr
onous memor
y r
ead/not write
103
IO Supply (DVpp)
104
EM_OE
O
–
N
SDRAM output enable
105
SPI0_ENA/I2C1_SDA
IO
–
Y
SPI0 enable (r
eady) or I2c1 serial data
106
Gr
ound(Vss)
107
SPI0_ENA/I2C1_SCL
IO
–
Y
SPI0 enable (r
eady) or I2c1 serial clock
108
SPI0_CLK/I2C0_SCL
IO
–
Y
SPI0 serial clock or I2c0 serial clock
109
Gr
ound(Vss)
110
SPI0_SIMO
IO
–
Y
SPI0 data pin slave in master out
111
SPI0_SOMI/I2C0_SDA
IO
–
Y
SPI0 data pin slave out master in or I2C0 serial data
112
IO Supply (DVpp)
113
AXR0[0]
IO
–
Y
McASP0 serial data 0
114
Gr
ound(Vss)
115
AXR0[1]
IO
–
Y
McASP0 serial data 1
116
AXR0[2]
IO
–
Y
McASP0 serial data 2
117
AXR0[3]
IO
–
Y
McASP0 serial data 3
118
Gr
ound(Vss)
119
AXR0[4]
IO
–
Y
McASP0 serial data 4
120
AXR0[5]/SPI1_SCS
IO
–
Y
McASP0 serial data 5 or SPI1 slave chip select
121
AXR0[6]/SPI1_ENA
IO
–
Y
McASP0 serial data 6 or SPI1 enable (r
eady)
122
AXR0[7]/SPI1_CLK
IO
–
Y
McASP0 serial data 7 or SPI1 serial clock
123
Cor
e Supply (CVpp)
124
Gr
ound(Vss)
No.
F
unction Name
TYPE
(1)
PULL
(2)
GPIO
(3)
Detail of F
unction
125
IO Supply (DVpp)
126
AXR0[8]/AXR1[5]/SPI1_SOMI
IO
–
Y
McASP0 serial data 8 or McASP1 serial data 5 or SPI1 data pin slave out master in
127
AXR0[9]/AXR1[4]/SPI1_SIMO
IO
–
Y
McASP0 serial data 9 or McASP1 serial data 4 or SPI1 data pin slave in master out
128
Cor
e Supply (CVpp)
129
Gr
ound(Vss)
IO
–
Y
130
AXR0[10]/AXR1[3]
IO
–
Y
McASP0 serial data 10 or McASP1 serial data 3
131
AXR0[11]/AXR1[2]
McASP0 serial data 11 or McASP1 serial data 2
132
Cor
e Supply (CVpp)
133
Gr
ound(Vss)
IO
–
Y
134
AXR0[12]/AXR1[1]
IO
–
Y
McASP0 serial data 12 or McASP1 serial data 1
135
AXR0[13]/AXR1[0]
McASP0 serial data 13 or McASP1 serial data 0
136
IO Supply (DVpp)
IO
–
Y
137
AXR0[14]/AXR2[1]
IO
–
Y
McASP0 serial data 14 or McASP2 serial data 1
138
AXR0[15]/AXR2[0]
IO
–
Y
McASP0 serial data 15 or McASP2 serial data 0
139
ACLKR0
McASP0 r
eceive bit clock
140
Gr
ound(Vss)
IO
–
Y
141
AFSR0
IO
–
Y
McASP0 r
eceive frame Sync (L/R clock)
142
ACLKX0
IO
–
Y
McASP0 transmit bit clock
143
AHCLKR0/AHCLKR1
IO
–
Y
McASP0 and McASP1 r
eceive master clock
144
AFSX0
McASP0 transmit frame Sync (L/R clock)