Yamaha Portable Grand YPG-635, Service Manual

Page: 23 / 81

23
DGX-630/YPG-635
CONTENTS
（目次）
● AK4385ET (X6040A01) DAC ....................................................................................... 26
● R8A02032BG (X8810A00) CPU (SWX02) ................................................................... 24
● S1D13700F01A100 (X5422A00) LCD CONTROLLER ............................................... 23
● UPD789022GB-A15-8E (XZ56010R) CPU (MKS) ....................................................... 23
■
LSI PIN DESCRIPTION
（LSI 端子機能表）
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
P12
P11
P10
P47/KR7
P46/KR6
P45/KR5
P44/KR4
P43/KR3
P42/KR2
P41/KR1
P40/KR0
NC
IC
X2
X1
VSS0
VDD0
/RESET
P53
P52
P51/TO2
P50/TI0/TO0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I/O
Port 1
Port 4/Key return signal detection input
Internally connected (N.C.)
Clock
Ground
Power supply
System reset
Port 5
Port 5/16-bit timer output
Port 5/External count clock input to 8-bit timer/8-bit timer output
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44 P32/INTP2/CPT2
P31/INTP1
P30/INTP0
P22/RXD/SI0
P21/TXD/SO0
P20/ASCK//SCK0
P07
P06
P05
P04
P03
P02
P01
P00
NC
VDD1
VSS1
P17
P16
P15
P14
P13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 3/External interrupt input/Capture edge input
Port 3/External interrupt input
Port 2/Asynchronous serial interface serial data input/Serial interface serial data input
Port 2/Asynchronous serial interface serial data output/Serial interface serial data output
Port 2/Asynchronous serial interface serial clock input/Serial interface serial clock
Port 0
Power supply
Ground
Port 1
UPD789022GB-A15-8E (XZ56010R) CPU (MKS)
DM: IC17
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
AB12
AB11
AB10
AB9
AB8
HIOVDD
AB7
AB6
AB5
AB4
COREVDD
AB3
AB2
AB1
AB0
VSS
FPDAT3
FPDAT2
FPDAT1
FPDAT0
NIOVDD
FPSHIFT
XECL
COREVDD
FPLINE
MOD
VSS
YSCL
FPFRAME
YDIS
NIOVDD
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
Ground
Address bus
Power supply
Address bus
Power supply
Address bus
Ground
Data bus
Power supply
Shift clock
X driver enable chain clock
Power supply
Latch pulse
Frame signal
Ground
Scan shift clock
Scan start pulse
LCD power-down output
Power supply
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64 VSS
XCD1
XCG1
RESET#
SCANEN
TESTEN
CLKI
COREVDD
RD#
WR#
CS#
DB7
DB6
DB5
DB4
HIOVDD
DB3
DB2
DB1
DB0
VSS
WAIT#
HIOVDD
CNF0
CNF1
CNF2
CNF3
CNF4
AS#
AB15
AB14
AB13
O
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
Ground
Drain output
Gate input
Reset
Test mode set up input
Externally sourced system clock
Power supply
Read strobe
Write strobe
Chip select
Data bus
Power supply
Data bus
Ground
Wait output
Power supply
Input pin for S1D 13700 setting
Address strobe
Address bus
S1D13700F01A100 (X5422A00) LCD CONTROLLER
DM: IC4