19
MX-D1
MX-D1
■
IC DATA
IC107: YDA133-E (MAIN P.C.B)
Digital Audio Power Amplifier Controller
GND
10 ICOUT
18 HIN
16 PVDD
19 HIP
17 PVSS
15 MUTEN
9 ERRIN
MUTE
ERROR
Control
circuit
20 MSSEL
22 MCKIO
23 XI
24 XO
21 CKOUT
Clock
part
Power supply
voltage
detection
circuit
Digital
modulation
circuit
PLL
Digital modulation part
Operational
amplifier
for integration
13
DETB
11
DETA
14
DETB2
12
DETA2
8
VSS
1
GND
7
VDD
6
AINP
3
SEL
2
PLLC
+
–
4
AX1
5
AINM
No.
Name
I/O
Function
1
GND
Ground
2
PLLC
AO
Connecting Loop Filter for Internal PLL
3
SEL
I
Test
4
AX1
AO
Precision Input Stage Operational Amplifier Output
5
AINM
AI
Precision Input Stage Operational Amplifier Inversion Input
6
AINP
AI
Precision Input Stage Operational Amplifier Non-inversion Input
7
VDD
Input Stage Analog Circuit Positive Power Supply
8
VSS
Input Stage Analog Circuit Negative Power Supply
9
ERRIN
I
Error Recognition Signal Input
10
ICOUT
OD
Error Recognition Signal Output
11
DETA
AI
Setting Reference Voltage for VPP and VMM Voltage Detection
12
DETA2
AI
Setting Open Loop Gain of Digital Amplifier
13
DETB
AIO
Connecting Capacitor for Setting Power Supply Tuning on Wait Time
14
DETB2
AI
Setting Digital Amplifier Open Loop Gain
15
MUTEN
I
Setting Mute
16
PVDD
Positive Power Supply for Output Buffer
17
PVSS
Negative Power Supply for Output Buffer
18
HIN
O
Digital Modulation Signal Inversion Output
19
HIP
O
Digital Modulation Signal Non-inversion Output
20
MSSEL
I
Changing Mode between Master and Slave
21
CKOUT
O
Local Power Supply Driving Clock Output
22
MCKIO
IO
Clock Input/Output
23
XI
I
5.6 MHz CERALOCK *
1)
Connection Input
24
XO
O
5.6 MHz CERALOCK *
1)
Connection Output
(Unconnected)
Note)
AO : Analog Output
AI
: Analog Input
AIO : Analog Input/Output
OD : Open Drain Output
PVDD and VDD are shortcircuited on the board.
PVSS and VSS are shortcircuited on the board.
GND is grounded on the board.
*
1)
CERALOCK of subsequent explanation is the registered trademark of Murata Manufacturing Co., Ltd.
