MR816CSX/MR816X
14
LSI PIN DESCRIPTION
（
LSI
端子機能表）
(Digital to Analog Converter) ................................................................20
(Analog to Digital Converter) ........................................................19
(MAIN/SUB) ......................................................................................18
(Gate Array) .............................................................................19
(Electric Variable Resistance 2) .........................................................20
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
IO
IO
IO
IO
IO
nCSO
DATA0
nCONFIG
VCCA_PLL1
CLK0
GNDA_PLL1
nCEO
nCE
MSEL0
MSEL1
DCLK
ASDO
VCCIO1
GND
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
VCCIO4
GND
VCCINT
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
VCCINT
GND
VCCIO4
IO
IO
IO
I/O
I/O
I/O
I/O
I/O
O
I
I
-
I
-
O
I
I
I
I/O
O
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
I/O
I/O
I/O
I/O
PAD[4]
PAD[3]
AVC_SCLK Data
I/Os
AVC_DATAI
AVC_CS
Chip select output that enables/disables a
serial configuration device.
Dedicated configuration data input pin
Dedicated configuration control input
Analog power for PLL1
Dedicated global clock input
Analog ground for PLL1
Output that drives low when device configu-
ration is complete.
Active-low chip enable
Dedicated mode select control pins that set
the configuration mode for the device.
Clock input (PS mode) or output (AS mode)
Active serial data output from the Cyclone device
I/O supply voltage pin for bank 1
Ground
P48V[8]
P48V[7]
P48V[6]
P48V[5]
P48V[4]
Data I/Os
P48V[3]
DA4358_CS
DA4382_CS
DA_CDTI
DA_CCLK
Ground
I/O supply voltage pin for bank 4
Ground
Internal logic array voltage supply pin
CLK18M
P48V[1]
PAD[1]
P48V[2]
PAD[2]
Data I/Os
Analog_MUTE
DSP_MUTE/DAC1_MUTE/
DAC2_MUTE
MUTE_REQ
MUTE_OFF
Ground
Internal logic array voltage supply pin
Ground
I/O supply voltage pin for bank 4
EN[1]
EN[2]
Data I/Os
EN[3]
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
IO
IO
IO
IO
IO
IO
IO
IO
GND
VCCIO3
CONF_DONE
nSTATUS
TCK
TMS
TDO
IO
CLK2
TDI
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VCCIO2
GND
VCCINT
GND
IO
IO
IO
IO
IO
IO
IO
IO
IO
VCCINT
GND
VCCIO2
GND
IO
IO
IO
IO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
-
-
I
I
O
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I/O
-
I/O
I/O
I/O
I/O
EN[4]
MMD[7]
MMD[6]
MMD[5]
Data I/Os
MMD[4]
MMD[3]
MMD[2]
MMD[1]
Ground
I/O supply voltage pin for bank 3
Dedicated configuration status pin
Dedicated JTAG input pin
Dedicated JTAG output pin
MMD[0]
Dedicated global clock input
Dedicated JTAG input pin
CD60RD
CS61WR
CS62WR
CS63WR
MMA[1]
MIRQ
Data I/Os
MCI_SIRQ
DICE_IRQO
DA_MUTE
DICE_MUTE
AES_MUTE/WCK_MUTE
FW_MUTE
I/O supply voltage pin for bank 2
Ground
Internal logic array voltage supply pin
Ground
FS_CLK
TL1
DODATA[2]
DODATA[1]
DIDATA[2] Data
I/Os
DIDATA[1]
DSAI_DO
DSAI_DI
DSAI_Fs
Internal logic array voltage supply pin
Ground
I/O supply voltage pin for bank 2
Ground
PAD[8]
PAD[7]
Data I/Os
PAD[6]
PAD[5]
EP1C3T100C8N
(X5691A00)
FPGA
Summary of Contents for MR816x
Page 26: ...26 MR816CSX MR816X DM Circuit Board B B 2NA WK58180 ...
Page 27: ...27 MR816CSX MR816X Component side 部品側 3 layer 3 層 Scale 70 100 B B 2NA WK58180 ...
Page 28: ...28 MR816CSX MR816X DM Circuit Board C C 2NA WK58180 ...
Page 29: ...29 MR816CSX MR816X Component side 部品側 6 layer 6 層 Scale 70 100 C C 2NA WK58180 ...
Page 30: ...30 MR816CSX MR816X DM Circuit Board D D 2NA WK58180 ...
Page 31: ...31 MR816CSX MR816X Pattern side パターン側 Scale 70 100 D D 2NA WK58180 ...
Page 33: ...33 MR816CSX MR816X Pattern side パターン側 G G G G H H PN Circuit Board H H 2NA WM06850 ...
