9
LMY2-MLAB
AK5392-VS-E2 (XV065A00) A/D CONVERTER
PIN
No.
NAME
I/O
FUNCTION
PIN
No.
NAME
I/O
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VREFL
GNDL
VCOML
AINL+
AINL-
ZCAL
VD
DGND
CAL
RST
SMODE2
SMODE1
LSCK
SCLK
O
O
I
I
I
O
I
I
I
I/O
I/O
L ch standard voltage output (+3.75V)
L ch standard grand (0 V)
L ch common voltage (+2.5 V)
L ch input
L ch analog -input
Zero calibration
"L"=VCOML, VCOMR
"H": Analog input (AINLI,AINRI)
Power supply for digital
Ground for digital
Calibration status
Reset
Serial interface mode select
Clock for L/R ch select
Serial data clock
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SDATA
FSYNC
MCLK
CMODE
HPFE
TEST
B GND
A GND
VA
AINR-
AINR+
VCOMR
GNDR
VREFR
O
I/O
I
I
I
I
I
I
O
O
Serial data output
Frame synchronization clock
Master clock input
Master clock select
HPF enable pin
Test pin
Ground (0 V)
Ground for analog (0 V)
Power source for analog (5V)
Rch analog -input
Rch input
R ch common voltage (2.5 V)
R ch standard glound (0 V)
R ch standard voltage output (3.75 V)
■
IC BLOCK DIAGRAM
（
IC
ブロック図）
SN74LV273APWR (X5074A00)
Octal 3-State D-Type Flip Flop
TC74VHC245FT (XU797A00)
Octal 3-State Bus Buffer
NJM2068MD-T2 (X3505A00)
Dual Operatinal Amplifier
ML2: IC100, 109, 200, 209
HIC-HA: IC101, 102
TC74VHC244FT (XW234A00)
Octal 3-State Bus Buffer
SN74LV138ANSR (IS013810)
DECODER
SN74LV08APWR (X4463A00)
Qual 2 Input AND
1
2
3
4
-V
8
7
6
5
Output A
+V
Non-Inverting
Input A
-DC Voltage Supply
+DC Voltage
Supply
Output B
Inverting
Input B
Non-Inverting
Input B
Inverting
Input A
+
-
+
-
ENABLEINPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H
H
H
L
H
H
H
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
X
X
X
L
L
L
L
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
X
X
L
H
H
H
H
H
H
H
H
X
H
X
L
L
L
L
L
L
L
L
X
X
X
L
H
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
SELECTINPUTS
OUTPUTS
GND
Vcc
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
GND
4Q
4D
3D
3Q
2Q
2D
1D
1Q
CLR
1
D1R
2
3
4
5
6
7
8
9
10
A1
A2
A3
A4
A5
A6
A7
A8
GND
11
12
13
14
15
16
17
18
19
20
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Q
Q
D
D
CK
CK
CL
CL
Q
Q
D
D
CK
CK
CL
CL
Q
Q
D
D
CK
CK
CL
CL
Q
Q
D
D
CK
CK
CL
CL
1
2
3
1A
1Y
4
2A
5
2B
6
2Y
7
VSS
1B
14
13
12
Vcc
4A
11
4Y
10
3B
9
3A
8
3Y
4B
1
2
3
4
5
6
7
A
B
Select
Enable
Output
B
C
C
G2A
G2A
G2B
G2B
G1
G1
Y7
Y7
16
15
14
13
12
11
10
Vcc
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Output
Y3
Y4
Y4
Y5
Y5
8
GND
9
Y6
A
Y6
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VDD (Vcc)
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
(GND) Vss
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