Yamaha HTR-6063, Service Manual

Page: 108 / 144

A
1
2
3
4
5
6
7
8
9
10
B C D E F G H I J K L M N
RX-V667/HTR-6063/RX-A700
108
DIGITAL 2/7
★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked ⚠ and must be replaced
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
CB31
CB34
CB32
IC33
IC36
IC40
IC39
IC37
IC38
IC31
IC32
IC41
1.8
1.9
3.3
3.3
0
3.3
1.8 1.8
1.8
0
0.6
0 0 0 0
1.8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1.8
0
3.3
1.1 1.7 1.8 0.6 0.5 0.5 0.4
3.3
1.9 1.9 1.9 1.8 3.3 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
3.3
0 0 0 0
0
3.3
1.8 0
1.6
1.5
3.3
3.3
1.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.7
3.3
3.3
3.1
3.1
0
3.3
3.3
1.5
1.5
1.9
0.4
0
0
0
0.4
0.4
0.5
0.5
3.3
1.8
0
1.8
0
1.6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.3
3.3
2.5
3.1
5.5
0 0 0 0 0 0 0 0 0
0.9 0.9 0.7 0.7 5.0
0
1.9
0.9
3.3
1.2 1.4 2.0
3.3
0 2.5 1.3 1.2 1.6 1.6
3.1
3.3 3.3 0 0
0
3.3 3.3 0.7
0.9
0.7
1.3
1.3
3.2
0
3.1
3.3
3.3
3.1
0
0
1.7
3.3
3.3
3.3
3.3
3.3
1.5
3.1
3.1
1.3
3.1
3.1
3.3
3.3
3.3
0
0
0
0
1.8 0
0 0
0
0
0
0
0
0
0
0
1.7
1.1
3.4
0.6
0.5
0.5
0.4
0
0
0
0
0
0
0
0
3.1
3.3
3.4
2.5
1.6
3.4
3.4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.1
3.3
2.6
1.7
0.6
0.5
0.5
0.4
1.7
1.2
POINT A XL31 (Pin 81 of IC32)
A
IC41 : ADV7172KSTZ
Digital PAL/NTSC video encoder
8
8
R
SET1
COMP1
ADV7172/ADV7173
COLOR
DATA
P0
V
REF
R
SET2
COMP2
P7
DAC E
DAC F
DAC D
DAC A
DAC B
DAC C
BRIGHTNESS AND
CONTRAST CONTROL
+
ADD SYNC
+
INTERPOLATOR
10
LUMA
PROGRAMMABLE
FILTER
+
SHARPNESS
FILTER
SATURATION CONTROL
+
ADD BURST
+
INTERPOLATOR
10
PROGRAMMABLE
CHROMA
FILTER
10
8
8
8
REAL-TIME
CONTROL CIRCUIT
SCRESET/RTC
MODULATOR
+
HUE
CONTROL
10
10
10
10
10
10
Y
U
V
8
4:2:2 TO
4:4:4
INTER-
POLATOR
10 10
SIN/COS
DDS BLOCK
DAC
CONTROL
BLOCK
DAC
CONTROL
BLOCK
10
10
10
10
10
10-bit
DAC
10-bit
DAC
10-bit
DAC
10-bit
DAC
10-bit
DAC
10-bit
DAC
10
M
U
L
T
I
P
L
E
X
E
R
M
U
L
T
I
P
L
E
X
E
R
YUV TO
RBG
MATRIX
+
YUV
LEVEL
CONTROL
BLOCK
I
2
C MPU PORT
HSYNC
FIELD/
VSYNC
BLANK
TTX
TTXREQ
V
AA
RESET
TELETEXT
INSERTION BLOCK
YCrCb
TO
YUV
MATRIX
CLOCK CSO_HSO VSO CLAMP SCLOCK SDATA ALSB
VIDEO TIMING
GENERATOR
GND
PAL_NTSC
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 37 43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AL
SB
HS
YNC
FIELD/VS
YNC
BLANK
GND
VAA
P0
P1
P2
P3
P4
P5
P6
P7
CSO_HSO
VAA
GND
V
AA
SCL
OCK
S
D
ATA
R
SET2
ADV7172/ADV7173
D
A
C F
COMP1
DAC A
VAA
DAC B
VAA
GND
VAA
DAC C
DAC D
VAA
GND
DAC E
CL
OCK
GND V
AA
VSO RESET P
AL_NTSC
CLAMP TTXREQ SCRESET/R
TC
R
SET1
V
REF
COMP2
GND
TTX
INPUT MUX
OUTPUT FIFO AND FORMATTER
IC32 : ADV7800BSTZ-80
10-bit, SDTV/HDTV 3D comb filter, video decoder and graphics digitizer
CLAMP
12
ANTIALIAS
FILTER
ADC
24
P30 TO P53
GRAPHICS RGB
AIN1
AIN12
CVBS
S-VIDEO
SCART-
(CBVS+RGB)
YPrPb
TO
CVBS OUT
FB
HS_IN2
VS_IN2
HS_IN
VS_IN
SOG
SOY
SCLK
SCLK2
SDA
SDA2
ALSB
INT
CLK_IN
DE_IN
10
CLAMP
ANTIALIAS
FILTER
ADC
10
CLAMP
ANTIALIAS
FILTER
ADC
10
2D COMB
CLAMP
DIGITAL INPUT PORT
DVI OR HDMI
SYNC PROCESSING AND
CLOCK GENERATION
SERIAL INTERFACE
CONTROL AND VBI DATA
COLORSPACE
CONVERSION
SSPD STDI
ANTIALIAS
FILTER
ADC
10
10
10
10
10
DAC
CORE
CLK
COMPONENT PROCESSOR (CP)
STANDARD DEFINITION PROCESSOR (SDP)
DDR/SDR-SDRAM INTERFACE
DDR/SDR-SDRAM INTERFACE
VBI DATA PROCESSOR (VDP)
GAIN
CONTROL
MACROVISION
DETECTION
ACTIVE PEAK
AND AGC
DIGITAL
FINE
CLAMP
AV CODE
INSERTION
OFFSET
CONTROL
LLC
SFL/SYNC_OUT
FIELD/DE
VS
CS/HS
PIXEL DATA
P0 TO P53
AV CODE
INSERTION
FAST BLANK
OVERLAY
CONTROL
VERTICAL
PEAKING
MACROVISION
DETECTION
HORIZONTAL
PEAKING
CTI
LTI ITOP
STANDARD
AUTODECTION
COLORSPACE
CONVERSION
525p/625p
SUPPORT
3D COMB
TBC
MUX
54
V DD
CE
Pin No.
1
2, 5
3
4
6
Symbol
V
OUT
GND
CE
NC
V DD
Description
Output Pin of Voltage Regulator
Ground Pin
Chip Enable Pin
No Connection
Input Pin
Vref
6 1
3 2,5
Current Limit
V OUT
GND
IC33 : R1172S331B-E2-F
CMOS-based positive-voltage regulator IC
1 DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
Vcc
OE
B1
B2
B3
B4
B5
B6
B7
B8
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
IC36-40 : SN74LVC245APWR
Octal bus transceivers with 3-state outputs
V
DD
CE
Vref
4 3
1 2
Current Limit
V
OUT
GND
Pin No.
1
2
3
4
Symbol
V OUT
GND
CE
V DD
Description
Output Pin
Ground Pin
Chip Enable ("H" Active)
Input Pin
IC31 : RP130Q181D-TR-F
Voltage regulator
To DIGITAL 6/7
To DIGITAL 3/7
To DIGITAL 1/7
DIGITAL (1)
VIDEO DECODER and I/P
VIDEO
ENCODER
to VIDEO (1)_CB304
Page 118 K9
to VIDEO (9)_CB391
(B, G, F models)
Page 120 C3