Yamaha HTR-5063, Service Manual

Page: 59 / 130

59
RX-V567/HTR-5063
RX-V567/HTR-5063
No.
Function Name
(P.C.B.)
TYPE
(1)
PULL
(2)
GPIO
(3)
Detail of Function
1 VSS
2 AHCLKX0/AHCLKX2 IO – Y McASP0 and McASP2 transmit master clock
3 AMUTE0 IO – Y McASP0 mute output
4 AMUTE1 IO – Y McASP1 mute output
5 AHCLKX1 IO – Y McASP1 transmit master clock
6 VSS
7 ACLKX1 IO – Y McASP1 transmit bit clock
8 CVDD
9 ACLKR1 IO – Y McASP1 receive bit clock
10 DVDD
11 AFSX1 IO – Y McASP1 transmit frame Sync (L/R clock)
12 AFSR1 IO – Y McASP1 receive frame Sync (L/R clock)
13 VSS
14 RESET IO – N Device reset pin
15 VSS
16 CVDD
17 CLKIN IO – N Alternate clock input (3.3-V LVCMOS input)
18 VSS
19 TMS IO IPU N Test mode select
20 CVDD
21 TRST IO IPU N Test reset
22 OSCVSS PWR – N Oscillator Vss tap point (for filter only)
23 OSCIN IO – N 1.2-V oscillator input
24 NC O – N
25 OSCVDD PWR – N Oscillator 1.2-V Vpp tap point (for filter only)
26 VSS
27 PLLHV PWR – N PLL 3.3-V supply input (requires external filter)
28 TDI IO IPU N Test data in
29 TDO OZ IPU N Test data out
30 VSS
31 DVDD
32 EMU[0] IO IPU N Emulation pin 0
33 CVDD
34 EMU[1] IO IPU N Emulation pin 1
35 TCK IO IPU N Test clock
36 Ground(Vss)
37 EM_CAS O – N SDRAM column address strobe
38 EM_WE O – N SDRAM write enable
39 EM_WE_DQM[0] O – N Write enable or byte enable for EM_D [7:0]
40 VSS
41 EM_D[7] IO – N EMIF data bus [lower 16-bits]
42 DVDD
43 EM_D[6] IO – N EMIF data bus [lower 16-bits]
44 CVDD
45 EM_D[5] IO – N EMIF data bus [lower 16-bits]
46 EM_D[4] IO – N EMIF data bus [lower 16-bits]
47 VSS
48 EM_D[3] IO – N EMIF data bus [lower 16-bits]
49 EM_D[2] IO – N EMIF data bus [lower 16-bits]
50 DVDD