71
RX-V467/HTR-4063
RX-V467/HTR-4063
Pin
No.
Port
Name
Function
Name
(P.C.B.)
I/O
Detail of Function
P
o
w
erOn
Stb
y Thr
h
Standb
y
Stb
ySleep
MCUSleep
[Sleep]
E8a,ICP
1
TXD4
IPD_MOSI
SO
O
O
O
O
iPod asynchronous data output
2
P9_5
NC
O
O
O
O
O
3
P9_4
NC
O
O
O
O
O
4
DA0
AMP_LMT
DA
I
I
I
I
Limiter control output
5
P9_2
O
O
O
O
O
(U, C, R, T, K, A, B, F, L, J models)
TB2in
RDS_RDY
TMR
O
O
O
[O]
RDS RRADY input
(G model)
6
RXD3
O
O
O
O
O
(U, C, R, T, K, A, B, F, L, J models)
RXD3
RDS_MISO
SI
O
O
O
O
RDS synchronous data input
(G model)
7
P90
O
O
O
O
O
(U, C, R, T, K, A, B, F, L, J models)
CLK3
RDS_SCK
SO
O
O
O
O
Synchronous clock output for RDS IC
Low level standby setting required
(G model)
8
INT8
IPD_DET
IRQ
IRQ
IRQ
IRQ
O
iPod detection / H -> L with iPod inserted into Dock
Restriction of port: INT for High Edge or Low Edge only
9
INT7
DIR_N_INT
IRQ
O
O
O
O
DIR interrupt
Restriction of port: INT for High Edge or Low Edge only
10 INT6
DSP_N_INT
IRQ
O
O
O
O
DA70Y interrupt
Restriction of port: INT for High Edge or Low Edge only
11
P143
O
O
O
O
O
(U, C, R, T, K, A, B, F, L, J models)
P143
RDS_N_RST
O
O
O
O
[O]
RDS reset
(G model)
12 VDC0
VDC0
MCU
MCU
MCU
MCU
MCU
13 P14_1
NC
O
O
O
O
O
14 VDC1
VDC1
MCU
MCU
MCU
MCU
MCU
15 NSD
NSD
MCU
MCU
MCU
MCU
MCU
4.7k PU / Debugger
16 CNVss
CNVss
MCU
MCU
MCU
MCU
MCU
Processor mode select Low: single chip mode
High: FLASH included boot mode
P50=H, P55=L when hardware resetting is cancelled
Standard serial input/output mode at CNVss=H
17 P8_7
DSP_N_CS
CS
O
O
O
O
DA70Y chip select
18 P8_6
DAC_N_CS
CS
O
O
O
O
DAC chip select
19 /RESET /RESET
MCU
MCU
MCU
MCU
MCU
Reset
20 Xout
Xout
MCU
MCU
MCU
MCU
MCU
8MHz ceramic oscillator
21 Vss
Vss
MCU
MCU
MCU
MCU
MCU
GND
22 Xin
Xin
MCU
MCU
MCU
MCU
MCU
8MHz ceramic oscillator
23 Vcc
Vcc
MCU
MCU
MCU
MCU
MCU
Microprocessor power supply
24 /NMI
/NMI
MCU
MCU
MCU
MCU
MCU
Unused, pulled up to Vcc
25 INT2
HDMI_MUT
IRQ
IRQ
O
O
O
HDMI MUTE input
H: Mute
26 INT1
HDMI_INT
IRQ
IRQ
O
O
O
Interrupt from HDMI RX
27 P8_2
DIR_SDO
I
O
O
O
O
DIR DATA input when in CDDA writing mode
28
P8_1
DSP_N_RDY
I
O
O
O
O
DA70Y RDY
P8_1
DIR_WCK
I
O
O
O
[O]
DIR_WCK input for CDDA writing
29 RXD5
DSP_MISO
SI
O
O
O
O
DIR, DA70Y, DAC synchronous data input
30 CLK5
DSP_SCK
SO
O
O
O
O
DIR, DA70Y, DAC synchronous clock output
31 TXD5
DSP_MOSI
SO
O
O
O
O
DIR, DA70Y, DAC synchronous data output
32 P7_5
DIR_N_RST
O
O
O
O
O
DIR reset
33 P7_4
DSP_FMT
O
O
O
O
O
DA70Y FULL MUTE output
H: Mute
34 P7_3
232C_MISO
I
I
I
I
I
Always set to input so as to use RXD1 at E8a
35 P7_2
SEL_CDDA
O
O
O
O
O
CDDA writing path select
H: CDDA writing mode L: Normal operation mode
36 SCL2
CEC_SCL
SO
SO
O
O
O
CEC microprocessor, Tuner, HDMI_EQ (SiI9185 A) I2C
SCL output
(100kHz device)
Pulled up to +3.3S by 3.3k in u-com block
37 SDA2
CEC_SDA
SIO
SIO
O
O
O
CEC microprocessor, Tuner, HDMI EQ (SiI9185 A) 12C
SCA input/output
(100kHz device)
Pulled up to +3.3S by 3.3k in u-com block
DRAFT
Summary of Contents for HTR-4063
Page 5: ...5 RX V467 HTR 4063 RX V467 HTR 4063 RX V467 T model RX V467 K model RX V467 A model DRAFT ...
Page 7: ...7 RX V467 HTR 4063 RX V467 HTR 4063 HTR 4063 R model HTR 4063 U model HTR 4063 C model DRAFT ...
Page 100: ...RX V467 HTR 4063 100 MEMO MEMO DRAFT ...
Page 133: ... ADVANCED SETUP RX V467 HTR 4063 134 DRAFT ...
Page 134: ...RX V467 HTR 4063 135 DRAFT ...
Page 135: ... 本機の設定を変更する RX V467 HTR 4063 136 DRAFT ...
Page 136: ...137 RX V467 HTR 4063 RX V467 HTR 4063 MEMO DRAFT ...
Page 137: ...RX V467 HTR 4063 DRAFT ...
