Yamaha EMX 660, Service Manual

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15
EMX660
LSI PIN DESCRIPTION
1 ED2 I/O 51 HX/SDA I/O/Z Host Interface Data Output/I2C Bus Data
2 ED3 I/O External Memory and I/O Data Bus 52 /EMPTY O/Z CMEM Update Buffer and HR Resistor Empty Flag Output
3 ED4 I/O 53 AXLR2 I Audio Data Transmitt Unit 2/3 Left and Right Channel Frame Frequency Signal
4 ED5 I/O 54 AR1 I Audio Data Receive Unit 1 Data Input
5 ED6 I/O 55 AR2 I Audio Data Receive Unit 2 Data Input
6 ED7 I/O 56 HRBCK/SA0 I Host Interface Receive Clock / I2C Bus Address 0
7 VSS - Ground 57 HR/SA1 I Host Interface Data Input/ I2C Bus Address 1
8 VDD - Power Supply 58 HRS/SA2 I Host Interface Receive Data Frame Frequency Signal/ I2C Bus Address 2
9 CLKM0 I Clock Mode 59 VSS - Ground
60 VDD - Power Supply
10 CLKM1 I 61 HXBCK/SCL I Host Interface Transmitt Clock/ I2C Bus Clock
11 TMS I TAP(Test Access Port) Mode Select 62 HXS/SA3 I Host Interface Transmitt Data Frame Frequency Signal/ I2C Bus Address 3
12 TDI I TAP Data Input 63 /CS/SA4 I Host Interface Chip Select/ I2C Bus Address 4
13 TCK I TAP Clock 64 HBCKS/SA5 I HRBCK/HXBCK Active Edge Select/ I2C Bus Address 5
14 CLKIN I Master Clock 65 I 2 CSEL I Host Interface Mode Select
15 VSS - Ground 66 VSS - Ground
16 VDD - Power Supply 67 VDD - Power Supply
17 CLKO O Machine Clock Output 68 AXBC1 I Audio Data Transmitt Unit 1 bit Clock
18 EA12/ED8 I/O 69 AXBC2 I Audio Data Transmitt Unit 2/3 bit Click
19 EA13/ED9 I/O External SRAM and ROM Address Bus/ External DRAM and I/O Data Bus 70 AXLR1 I Audio Data Transmitt Unit 1 Left and Right Channel Frame Frequency Signal
20 EA14/ED10 I/O 71 DIV8 O Machine Clock Output then 8 min.
21 EA15/ED11 I/O 72 /LAV O Ruch ALU Overflow Frag Output
22 VSS - Ground 73 /LMV O Ruch MAC Overflow Frag Output
23 VDD - Power Supply 74 /DRDY O/Z Host Interface Transmitt Data Ready Frag Output
24 EA16/ED12 I/O 75 EMU0 I/O/Z Emurator Interrupt 0
25 EA17/ED13 I/O External SRAM and ROM Address Bus/ External DRAM and I/O Data Bus 76 EMU1 I/O/Z Emurator Interrupt 1
26 EA18/ED14 I/O 77 TDO O/Z TAP(Test Access Port) Data Output
27 EA19/ED15 I/O 78 DIV512 O Machine Clock then512 min.
28 EA4/ED16 I/O 79 ARLR1 I Audio Data Receive Unit 1 Left and Right Channel Frame Frequency Signal
29 EA5/ED17 I/O External Memory Address Bus/ External I/O Data Bus 80 ARLR2 I Audio Data Receive Unit 2 Left and Right Channel Frame Frequency Signal
30 EA6/ED18 I/O 81 HDIR/SA6 I Host Interface Data Format Select/ I2C Bus Address 6
31 EA7/ED19 I/O 82 SEL5V3V I Input Level Control
32 VSS - Ground 83 /MUTE I Mute Control
33 VDD - Power Supply 84 /TRST I TAP(Test Access Port) Reset
34 EA8/ED20 I/O 85 /RS I Hardware Reset
35 EA9/ED21 I/O External Memory Address Bus/ External I/O Data Bus 86 VSS - Ground
36 EA10/ED22 I/O 87 VDD - Power Supply
37 EA11/ED23 I/O 88 /IOE O External I/O Enable
38 TEST0 I 89 /RAS/SRCS O External DRAM Low Address Strove/External SRAM Chip Select
39 TEST1 I Test Mode Control 90 /CAS/SROE O External DRAM Culumn Address Strove/External SRAM Output Enable
40 TEST2 I 91 /ROME O External ROM Enable
41 TEST3 I 92 /WE O External Memory and I/O Wright Enable
42 /BIO I Separate Control Input 93 EA0 O
43 /INT1 I Interrupt 1 94 EA1 O External Memory and I/O Address Bus
44 ARBC1 I Audio Data Receive Unit 1 bit Clock 95 EA2 O
45 ARBC2 I Audio Data Receive Unit 2 bit Clock 96 EA3 O
46 AX1 O Audio Data Transmitt Unit 1 Data Output 97 VSS - Ground
47 AX2 O Audio Data Transmitt Unit 2 Data Output 98 VDD - Power Supply
48 AX3 O Audio Data Transmitt Unit 3 Data Output 99 ED0 I/O External Memory and I/O Data Bus
49 VSS - Ground 100 ED1 I/O
50 VDD - Power Supply
PIN
NAME I/O FUNCTION
NO.
PIN
NAME I/O FUNCTION
NO.












ZFX-2 (XY297A00) DSP















SUB: IC306


































1 min. 3fold 5fold PLL BYPASS
CLKM0 0 1 0 1
CLKM1 0 0 1 1
Z: High inpedance